JPS5976468A - Semiconductor device - Google Patents

Abstract

PURPOSE:To securely position a diffused region at the center in an aperture by a method wherein a thick field insulation film is adhered on a semiconductor substrate, the aperture is bored in correspondence to the diffused region, which region is formed by plasma ion implantation when it is formed at a substrate surface layer part exposed in the aperture. CONSTITUTION:The thick field insulation film 2 is adhered on the semiconductor substrate 1, and the open hole parts 10 and 9 are bored in correspondence to the diffused regions 6 and 9 to be formed. Next, the diffused regions 6 and 9 are formed at the surface layer part of the substrate 1 exposed by utilizing these open holes 10 and 9; thereat, these regions are formed by plasma ion implantation. In this manner, the regions 6 and 9 are securely coincident to the centers of the open hole parts 10 and 9; when leads 5 and 3 are adhered on these regions while they are made to run along or buried in the side wall of the film 2, there is no possibility of the positional slippages thereof. At this time, it is better to use Al, Mo, W, etc. for the leads 5 and 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention involves selectively doping impurities with K, valence, or V valence into a semiconductor using plasma ion implantation (hereinafter referred to as PAE), and adding impurities onto the apertures where the impurities have been added. The present invention relates to a semiconductor device and a method for manufacturing the same, the purpose of which is to form semiconductor or conductor films or leads on other insulating materials using plasma vapor deposition (hereinafter referred to as PCVD).

In this invention, in particular, since the film is formed uniformly on the side surfaces of the hole to the same thickness as on the flat surface, there is no possibility of a decrease in reliability with respect to the step coverage (step coverage) K.
In particular, when the size of this hole is set to 2μ or 1.5μ, a semiconductor or conductor film can be formed with a sufficient level difference even if the film thickness of the film is 0.5μ or 1p. As a result, lead wires with a width of 0.5-1μ can be made with a tolerance of ±0.2μ. Therefore, it has extremely excellent characteristics for VLSI (super I, Sυ).

Furthermore, in the present invention, even if there is a misalignment between the impurity region of the lower lead (fC) and the lead above it due to mask alignment accuracy, an impurity region by KP can be provided between them to electrically connect them. Furthermore, this impurity region prevents the semiconductor from directly contacting the lead and causing junction leakage. Therefore, the alignment accuracy at the contact part can be substantially made to have a self-line configuration in accordance with the alignment percentage of the leads, and the accuracy between the two-layer wiring can be improved by 1±0.5μ, instead of the conventional precision of 300.5μ. It has the feature that the contacts can be made with sufficient ohmic contact.

FIG. 1 shows a vertical sectional view of a conventional example.

A field insulator (2) was provided on the semiconductor (1), and contacts were to be formed with the open-hole narrow regions (6) and (7). However, in such a configuration, the hole of the opening (10) must be located at the center of the impurity region (6) and the size of the hole must be small, and good ohmic contact cannot be guaranteed.

For example, in Figure 1 (37), the lead (3) and the substrate semiconductor (1) were short-circuited, causing leakage in the opposite direction.Furthermore, the lead was connected to the field insulator (2) side. In parts (8) and (4), when this lead is made by vacuum evaporation of aluminum, it is not thick enough, and as a result, it is easy to break the wire at the stepped part on the side, resulting in a thickness of 1 to 2 μm. It was not possible to construct a contact area with a sufficiently thin line for the width of the pillow. In particular, the slopes that are not formed on the sides of the leads of such main trunks can be avoided by forming the conductor layer (5) for the series leads by vacuum evaporation, and by forming the field insulator (2) with a diameter of 1 to 2.5μ and a hole diameter of is 1
The present invention relates to a semiconductor device and its πM manufacturing method for further promoting ohmic contact at the contact portion.

The details will be explained below according to the drawings.

FIG. 2 shows the manufacturing process of the present invention.

In the drawings, a compound semiconductor (P-type) such as single crystal silicon or gallium arsenide is used as the semiconductor. Furthermore, an insulator (2) is formed on the upper surface by LPCI7D (low pressure vapor phase method) or PCvD method, for example, by oxidation. Silicon and silicon nitride were formed to a thickness of 0.5-2μ.

Furthermore, the hole αO) is formed using photolithography technology.
(9) was established. (10) is 1μ゜, and (9) is 5μ0.

Next, as shown in FIG. 2(A)K, a P-e process was performed to form an impurity region of the opposite conductivity type (in this case, N type).

That is, such a semiconductor was placed in a plasma device and evacuated to 107 torr. The semiconductor was further heated to 200-300°C to remove adsorbed matter. After this, use hydrogen or helium for 100~3000
PPM K diluted reactive gas 7 Oshin or Arsine is introduced, plus 100 KH2~13,56
Plasma was generated by applying electrical energy of MHz high frequency or 7.45 GHz microwave. The reaction takes place in a plasma reactor (857, 9, 25 applications 9% 4 rj! 5
7-/(72go//672'ifl) J
-Q Futsu 2e When the phosphorus material becomes plasma, arsenic is ion-implanted into the semiconductor at a concentration of K 200-2000^, and this PAE implants a large amount of phosphorus or arsenic ions into the substrate, so it is processed by adding k bias. You can leave it there.

After carrying out such P-E for 5 to 30 minutes, the plasma discharge is stopped, the introduction of the reactive gas is also stopped, and further plasma discharge is carried out again with hydrogen to be injected into the semiconductor. Adsorbed matter was also removed by vapor phase etching.

Next, as shown in FIG. 2, a semiconductor or conductor was formed on this upper surface.

Specific example 1 When forming a non-single crystal silicon film, silane (100
%) into the same plasma reactor and similarly applied a high frequency of 30 W to perform plasma CVD, or As
H, ) /s iH4·0.5 to 1 to improve conductivity.

A semiconductor film was thus formed. Thereafter, the leads (3) and (5) were formed by etching using a conventional photolithography technique as shown in FIG. 2(B).

Concrete Example 2 As in Concrete Example 1, a semiconductor film was formed in the same reactor as shown in FIG. But 0
) As shown in K, it was possible to form the wire without any breakage at the stepped portion.

Concrete Example 3 In Fig. 2 (B), aluminum was formed by POVD using TMA (1 (a)) to a thickness of Od 2μ, and a conductor film with the same thickness as the upper surface was obtained. .

Specific example 4 In Fig. 2 (B), in addition to TMAK, Pm /TMA
= Added at a value of 0.1 to 1 inch. Furthermore, silane was added as S1 Yong/TMA 1-5%. In such a case, 1 to 5 silicon is added to the conductor, and 0.1 to 1 phosphorus is added to the conductor.
is added. Even in the subsequent heat treatment, such a conductor has a bonding area of 100-200% at the P work below.
Even when reduced to zero, no spikes were generated in the metal part, and the silicon semiconductor was not eaten away and frozen, making it possible to create a so-called shear-low junction.

If this was done using the electron beam evaporation method, it would be difficult to control the flow rate due to the difference between silicon and aluminum, but 1 was able to be produced without any difficulty in controllability.

Specific example 5 1NLnrl 7yr heat resistant reverse conductivity type coating at substrate temperature 200-30
It was possible to make it at 0°C.

The P1 14f 4 impurity region is extremely shallow (1oo
-2oo) Is it possible to make an ohmic contact or a junction of Q?

Concrete Example 6 In Figure 2 (B), it was possible to capture hydrogen from lead C and SiH. The characteristics were similar to those of Example 5.

In a specific example, Fig. 2 (B), wIF, day 1, and KP horse are P.
Introduced at 1 town = 0.5% K, WF, /SiH,
=1:'1 to 1:3 When 0 was introduced at K, phosphorus' was added and B i XW7 of 0.1-0.5μ could be obtained. Further, semiconductor layers of Tonoyo p and PH were laminated to form 0.1-0.3 μm.

Concrete Example 8 Among Concrete Examples 1-/7, an insulator such as silicon nitride was further laminated by the reaction of the same plasma OVD device.These insulators can be used as a mask in the photoetching process. .

As mentioned above, in specific examples 1 to 8, conductors or semiconductors are
After the etching, polymorphism was formed using the POVD method.

In this way, a conductor or a semiconductor can be freely formed on the side surface of the contact hole (opening part) of -5p to 5μ.

After further photolithography, the ohmic contact was made to p”4.
In order to achieve this, heat treatment was performed at a temperature of 3°C to prevent damage caused by PAE, and was effective in lowering the contact resistance.

FIG. 3 shows another vertical sectional view of the present invention.

Specific examples 1 to 8 are effective as in FIG. 2. Further, in the drawing, a first impurity region (38) of A-toge conductivity type is provided on the semiconductor (1) at a depth of O,'l-0,5μ, and an insulating layer is further formed on the upper surface of the impurity region (38). (2) is provided, and the insulator is provided with two openings (9), (10), and (39). Furthermore, the second impurity region (
6), ('1), Ql) are of the same conductivity type as the first impurity region and are provided at a depth of 200 to 2000 degrees.

In addition, in contact with the impurity region of the PET, there is a half-open hole in the contact part.The first impurity region 0→the smaller second impurity region
This is a contact portion of a two-layer wiring in which an impurity region Qυ is provided in the same shape as the hole, and a lead (A) is provided covering all the holes.

The opening (9) in FIG. 3 is specifically disclosed in the present invention. That is, the first impurity region 0→ is partially exposed in the hole (9), and the second impurity region (
7) and a part of it is in contact only at θno.

Furthermore, the semiconductor or conductor lead (3) is the second
is fused only with the impurity region (7) of the first impurity region α
It is separated from the barrel (IQ), that is, the first impurity region () of P is connected to the lead (3) and the cross-under-lead provided to the other first impurity region, 44
/&.

That is, as shown in the present invention Vζ, even when the lead (3) covers only a part of the hole, PIIK is applied to the entire surface of the hole.
Since more impurities are implanted, there is no problem at all in achieving contact. That is, with the same plasma device, P
This was achieved for the first time using an ion implanter that can achieve 2 to 4 times the ion concentration compared to conventional ion implantation equipment. A major feature of this method is that it is possible to generate multiple layers at once using a low-cost plasma device.

In Fig. 3, the hole 0→ is the impurity region (6) of PAE and the first impurity region θ, which are in contact with each other at the top, but the lead (5) is opened at 00N. I haven't filled it enough.

Even such a contact has the characteristic that reliability does not deteriorate at all.

FIG. 4 shows an application of the present invention to an insulated gate field effect semiconductor device. That is, in the drawing, a semiconductor (1) K is provided with a buried field insulator Q1). Further, a gate insulator () and a gate electrode (c) are provided on its upper surface. After forming the lead (c) with the same material as the gate electrode by introducing cylindrical
In PIIK, arsenic is implanted and the source (c) and drain layers are stacked.Additionally, according to the conventional ion implantation method, a high concentration of 00'' to 10''crrr') is implanted.
However, according to the present invention, injection can be performed by simply immersing in a plasma atmosphere of AeH and hydrogen or helium for ~10 minutes,
Its major feature is that it is inexpensive and can be mass-produced.

The source and drain pressure inside the reactor is 0.1 min rr.

AsH,/H,=1%, 300'O, high frequency output 5
0W It was possible to perform locm' [Pae of 4 in 10 minutes. In particular, even if the gate insulator (a) was formed to a thickness of 200 to 500 mm, it was possible to implant impurities with high purity.

In the drawing, the P process Q (31) is coated, a hole is made, and the contact (30) is connected using another P process.
: on its leads) are formed by the method of the present invention. Thus, the GFET or its integrated VLSIN
4-1 It is now possible to have a shallow joint with a depth of 20mm and a depth of 2000mm with a depth of 5μ. .

Furthermore, in the present invention, the semiconductor is not only silicon, but also gallium arsenide and aluminum gallium arsenide, since i and rlfi at low temperatures are not possible. , it can also be applied to light-receiving elements.

[Brief explanation of drawings]

FIG. 1 is a vertical sectional view showing a conventional semiconductor device. FIG. 2 shows the manufacturing process of the semiconductor device of the present invention. 3 and 4 show vertical sectional views of the semiconductor device of the present invention. 112 ヱ′°〜E− 12■

Claims (1)

[Claims] 1. A first impurity region provided in a semiconductor with an opposite conductivity type; an opening provided in an insulator on the semiconductor partially in contact with the impurity region; a second impurity region having approximately the same shape as the opening and the same conductivity type as the impurity region; a semiconductor or conductor contact that makes ohmic contact and is provided at least partially in contact with the impurity region; A semiconductor device 02 characterized in that a contact and a lead made of the same material extending on the insulator are provided, and in claim 1, the conductor making ohmic contact is made of aluminum, molybdenum, tungsten, A semiconductor device characterized by being selected from SixMoy (5ixty).