JPH0257700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention selectively adds valent or valent impurities into a semiconductor by plasma ion implantation (hereinafter referred to as PII), and insulates the holes above the added holes and other areas. Plasma vapor phase method (hereinafter referred to as
This invention relates to a semiconductor device that is intended to be formed by PCVD (PCVD) and a method for manufacturing the same.

In this invention, since the film is uniformly formed on the side surfaces of the hole to the same thickness as on the flat surface, there is no possibility of a decrease in reliability at step coverage. Even if the hole size is 2 μm or 1.5 μm and the film thickness is 0.3 to 1 μm, a semiconductor or conductor film can be formed with a sufficient level difference. As a result, the lead wire with a wire width of 0.5 to 1μ
We were able to make it with a tolerance of 0.2μ. Therefore,
It has extremely excellent characteristics for VLSI (Very LSI).

Furthermore, in this invention, even if there is a misalignment between the lower lead or impurity region and the lead above it due to mask alignment accuracy, an impurity region made of PII can be provided between the lower lead or impurity region and the lead above it to electrically connect the lead, and The region prevents the semiconductor and the lead from directly contacting each other and causing junction leakage. Therefore, the alignment precision of the leads, especially at the contact part, can essentially have a self-aligned configuration, and instead of the conventional precision of 3±0.5μ, a precision of 1±0.5μ is enough to make contact between two layers of wiring. It has the feature of being able to make a good ohmic contact.

FIG. 1 shows a vertical sectional view of a conventional example.

A field insulator 2 is provided on a semiconductor 1, and openings 9 and 10 are formed, and contacts are to be formed in the holes with impurity regions 6 and 7 in the semiconductor. However, in such a configuration, the hole 1
The position of the hole No. 0 was in the center of the impurity region 6, and the size of the hole had to be small, so good ohmic contact could not be guaranteed.

For example, in FIG. 137, the lead 3 and the substrate semiconductor 1 were short-circuited, causing leakage in the reverse direction bias. Furthermore, the leads do not have sufficient thickness at the sides 8, 4 of the field insulator 2 when they are made by vacuum evaporation of aluminum, and as a result, disconnections tend to occur at the stepped portions on these sides. Therefore, it was not possible to construct a contact region having a sufficiently thin line with a line width of 1 to 2 μm. Particularly, there is a tendency that the lead conductor layer 5 is not formed on the sides of the lead 8, and the field insulator 2 is formed by the vacuum evaporation method.
~2.5μ, and was significant when the hole diameter was 1 to 3μ.

The present invention relates to a semiconductor device and a method of manufacturing the same for further promoting ohmic contact at such a contact portion.

The details will be explained below with reference to the drawings.

FIG. 2 shows the manufacturing process of the present invention.

In the drawings, the semiconductor is, for example, single crystal silicon or a compound semiconductor such as gallium arsenide (P
type) was used. Furthermore, insulator 2 is placed on this top surface.
By LPCVD (low pressure vapor phase method) or PCVD method,
For example, silicon oxide or silicon nitride is formed to a thickness of 0.5 to 2 μm. Furthermore, openings 10 and 9 were provided using photolithography technology. 10 is 1μ〓, 9 is 5μ□
It is.

Next, as shown in FIG. 2A, a PII process was performed to form an impurity region of the opposite conductivity type (in this case, N type).

That is, such a semiconductor was placed in a plasma device and evacuated to 10 ^-7 torr. The semiconductor was further heated to 200 to 300°C to remove adsorbed substances. After this, 100~ by hydrogen or helium
Introducing reactive gas phoscine or arsine diluted to 3000PPM, plus 100KHz~
Plasma was created by adding 13.56MHz high frequency or 7.45GHz microwave electrical energy. The reaction was carried out using a plasma reactor (patent application filed on September 25, 1982).
167280/167281 (see Japanese Unexamined Patent Publication No. 59-56725/56726)).

Then, plasma-formed phosphorus or arsenic is ion-implanted into the semiconductor at a concentration of 200 to 2000 Å.
Since PII implants a large amount of phosphorus or arsenic ions into the substrate, a negative bias may be applied.
After performing PII in this manner for 5 to 30 minutes, the plasma discharge was stopped, the introduction of reactive gas was also stopped, and
Further, plasma discharge may be performed again using hydrogen to inject it into the semiconductor. Adsorbates were also removed by gas phase etching.

Next, as shown in FIG. 2, a semiconductor or conductor was formed on this upper surface.

Specific example 1 When forming a non-single crystal silicon film, introduce silane (100%) into the same plasma reactor, apply high frequency of 20 to 30 W, and perform plasma CVD to form a film with a thickness of 0.3 to 1μ. I let it happen. At this time, boron, phosphorus or arsenic is added to this semiconductor as B ₂ H ₆ ,
By PH ₃ or AsH ₃ (B ₂ H ₆ , PH ₃ or
The conductivity may be improved by introducing AsH ₃ )/SiH ₄ =0.5 to 1%.

A semiconductor film was thus formed. Thereafter, the leads 3 and 5 were etched using a conventional photolithography technique as shown in FIG. 2B.

Concrete Example 2 Similar to Concrete Example 1, as shown in Figure 2C,
A semiconductor film was formed in the same reactor. However, in this case, the thickness of the semiconductor film was set to 200 to 1000 Å. However, as shown in C, the step could be formed without any disconnection.

Specific Example 3 In FIG. 2B, aluminum was formed using TMA (Al(CH ₂ ) ₃ ) to a thickness of 0.5 to 2 μm by the PCVD method. For the high frequency of 13.56 MHz, 3 to 5 W is sufficient, and the temperature of the substrate was set to room temperature to 100°C. 250
It may be formed by LPCVD method at a temperature of .degree. C. to 350.degree. A conductive film with the same thickness as the top surface could be obtained at the stepped portion.

Specific example 4 In Figure 2B, in addition to TMA, PH ₃ /
It was added at a value of TMA=0.1-1%. More silane
It was added as SiH ₄ /TMA=1 to 5%. In such a case, the conductor is doped with 1 to 5% silicon and 0.1 to 1% phosphorus. Such a conductor is
Even in the subsequent heat treatment, even if the bonding area in the underlying PII is reduced to 100 to 2000 Å, no metal spikes will occur, and the silicon semiconductor will not be eaten away, so-called shear-low junctions. I was able to make it.

When this was done using electron beam evaporation, it was difficult to control the flow rate because of the difference between silicon and aluminum. In the PCVD method of the present invention, mixtures of two or three types could be made without any controllability difficulties.

Specific Example 5 In FIG. 2B, PCVD was performed by introducing WF ₆ or WF 6 and SiH ₄ using a carrier gas of hydrogen. As a result, a heat-resistant reverse conductivity type film of W or SixWy could be produced at a substrate temperature of 200 to 300°C.

We were able to create extremely shallow (100-200 Å) ohmic contact junctions with the impurity regions made with PII.

Specific example 6 In Figure 2B, MoCl ₃ or this and SiH ₄
By introducing hydrogen as a carrier gas, Example 1
PCVD was performed in the same manner. Then Mo or
We were able to create a heat-resistant conductor called SixMoy. The characteristics were similar to those of Example 5.

Example 7 In Figure 2B, PH ₃ is added to WF ₆ and SiH ₄ .
Introduced at PH ₃ /SiH ₄ = 0.5%, WF ₆ /SiH ₄ =
It was introduced at a ratio of 1:1 to 1:3. Then, phosphorus was added and it was possible to obtain 0.1 to 0.5μ of SixWy. Furthermore, a semiconductor layer of SiH ₄ and PH ₃ was laminated on the upper or lower surface to form a 0.1 to 0.3 μm layer.

Specific example 8 Among specific examples 1 to 7, the same plasma CVD
With different equipment and plasma CVD equipment,
SiH ₄ +NOx (x=0.5, 1 or 2) on this top surface
An insulator made of silicon oxide produced by the reaction of SiH 4 +NH ₃ or silicon nitride produced by the reaction of SiH ₄ +NH 3 was laminated. These insulators can be used as masks in the photoetching process.

As described above, in Examples 1 to 8, conductors or semiconductors were formed by the PCVD method after PII.

By doing this, it was possible to freely form a conductor or semiconductor on the side surface of a contact hole (opening part) of 0.5 .mu.m to 5 .mu.m.

Furthermore, after photolithography, heat treatment at a temperature of 300 to 700° C. to promote ohmic contact was effective in preventing damage caused by PII and further lowering contact resistance.

FIG. 3 shows another vertical sectional view of the present invention.

Specific examples 1 to 8 are effective as in FIG. 2. Further, in the drawing, a first impurity region 38 of a different conductivity type is provided on the semiconductor 1 at a depth of 0.1 to 0.5 μm, and an insulator 2 is provided on the upper surface of the first impurity region 38, and an opening is formed in the insulator. Holes 9, 10, and 39 are provided. In addition, the second
Impurity regions 6, 7, and 21 are of the same conductivity type as the first impurity region and are provided at a depth of 200 to 2000 Å. In addition, in contact with this PII impurity region, a semiconductor or conductor lead 5,
3,20 are provided.

In the drawing, the hole 39 is a very general hole, and a second impurity region 21 smaller than the first impurity region 18 is provided in the same shape as the hole, and the lead 20 is provided to cover all of this hole. This is the contact part of the two-layer wiring provided with.

The aperture 9 in FIG. 3 is particularly disclosed in the present invention. That is, the first impurity region 18 is exposed in a part of the hole 9 and is in contact with the second impurity region 7 provided by PII only in a part 17 thereof. Furthermore, the semiconductor or conductor lead 3 contacts only the second impurity region 7 of the PII and is spaced 16 from the first impurity region 18 . That is, the first PII
The impurity region 7 interconnects the lead 3 with a cross-under lead provided by another first impurity region.

That is, as shown in the present invention, even when the lead 3 covers only a part of the hole, it covers the entire surface of the hole.
Since impurities are implanted using PII, there is no problem at all in achieving contact. In other words, it was possible for the first time to perform PII and PCVD using the same plasma equipment, and it was achieved using an ion implantation equipment that can achieve an ion concentration 2 to 4 times that of conventional methods. A major feature of this method is that it is possible to generate multiple layers at once using a low-cost plasma device.

The hole 15 in FIG. 3 is the impurity region 6 of PII and the
It is also partially in contact with the impurity region 19 .
However, lead 5 does not sufficiently fill the opening at 15. Even such a contact has the characteristic that it does not cause any reduction in reliability.

FIG. 4 shows an application of the present invention to an insulated gate field effect semiconductor device.

That is, in the drawing, the semiconductor 1 is provided with a buried field insulator 21. Furthermore, a gate electrode 25 is provided on the gate insulator 22 and its upper surface. After the lead 26 is formed from the same material as the gate electrode 25 by introducing phosphorus, arsenic is implanted by PII and the source 28 and drain 29 are laminated.

This is because conventionally known ion implantation methods require implantation at a high concentration (10 ¹⁹ to 10 ²¹ cm ^-3 ) for as long as one hour. However, the present invention has the great feature that it can be injected by simply immersing it in a plasma atmosphere of AsH ₃ and hydrogen or helium for about 10 minutes, and that it can be mass-produced at low cost.

The source and drain pressure inside the reactor is 0.1torr.
PII with a high concentration of 10 ²⁰ cm was possible at AsH ₃ /H ₂ = 1%, 300°C, and high frequency output of 50W for 10 minutes. In particular, even if the gate insulator 22 was formed to a thickness of 200 to 500 Å, implantation of impurities with such high purity was possible.

In the drawing, a coating of PIQ 31 is applied, a hole is provided, a contact 30 is made of another PII, and its lead 27 is formed by the method of the present invention.

Thus IGFET or its integrated VLSI
Also, it has become possible to make the channel 0.2 to 0.5 μ and have a shallow junction with a junction depth of 200 to 2000 Å.

Furthermore, in the present invention, the semiconductor is not only silicon, but also gallium arsenide and aluminum arsenide, since it can be processed at low temperatures. It is also applicable to

[Brief explanation of drawings]

FIG. 1 is a vertical sectional view showing a conventional semiconductor device. FIG. 2 shows the manufacturing process of the semiconductor device of the present invention. 3 and 4 show vertical sectional views of the semiconductor device of the present invention.

Claims (1)

[Scope of Claims] 1. A semiconductor device having a semiconductor and an insulator having an opening on the semiconductor, the semiconductor surface being exposed in the opening, is disposed in a plasma processing apparatus, and an electrical forming an impurity region by plasma ion implantation of a valence or valence impurity into the semiconductor in the opening by applying energy and exposing the valence or valence impurity to a reactive gas atmosphere; After this step, a reactive gas of the conductor or semiconductor is introduced into the same reactor, and impurities on the insulator and in the opening are decomposed and reacted by plasma vapor phase method or reduced pressure vapor phase method. 1. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed on a region. 2. The method for manufacturing a semiconductor device according to claim 1, characterized in that an impurity of the same conductivity type as that added by plasma ion implantation is added into the conductor or semiconductor.