JPS5972752A - High frequency transistor - Google Patents
High frequency transistorInfo
- Publication number
- JPS5972752A JPS5972752A JP18500482A JP18500482A JPS5972752A JP S5972752 A JPS5972752 A JP S5972752A JP 18500482 A JP18500482 A JP 18500482A JP 18500482 A JP18500482 A JP 18500482A JP S5972752 A JPS5972752 A JP S5972752A
- Authority
- JP
- Japan
- Prior art keywords
- bias
- package
- high frequency
- terminals
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Microwave Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はバイアス回路を内蔵し、複数個のバイアス端
子を設けた高周波トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high frequency transistor incorporating a bias circuit and having a plurality of bias terminals.
第1図は従来のバイアス回路)よびバイアス端子付き高
周波トランジスタを示す平面図である。FIG. 1 is a plan view showing a conventional bias circuit and a high frequency transistor with a bias terminal.
同図において、(1)はバイアス回路を内蔵したセラミ
ックなどからなるパッケージ、C2)はこのノくツケー
ジ(1)内でトランジスタの入力電極に接続し、このパ
ッケージ(1)の−側部に延長した導電板からなる入力
電極リード、(3)はこのパッケージ(1)内でトラン
ジスタの出力電極に接続し、前記入力電極リード(2)
と反対方向に延長した導体板からなる出力電極リード、
(4)および(5)はこのパッケージ(1)内でトラン
ジスタの共通電極に接続し、入力電極リード(2)およ
び出力電極リード(3)の中央部からそれぞれ両側部へ
延長した導体板からなる共通電極リード、(6)はこの
パッケージ(1)内でバイアス回路を介してトランジス
タの入力電極に接続した入力電極用バイアス端子、CI
)はとのパッケージ(1)内でバイアス回路を介してト
ランジスタの出力電極に接続した出力電極用バイアス端
子である。In the figure, (1) is a package made of ceramic or the like with a built-in bias circuit, and C2) is connected to the input electrode of the transistor within this socket cage (1) and extended to the negative side of this package (1). The input electrode lead (3) consisting of a conductive plate is connected to the output electrode of the transistor within this package (1), and the input electrode lead (2) is connected to the output electrode of the transistor in this package (1).
an output electrode lead consisting of a conductor plate extending in the opposite direction;
(4) and (5) are connected to the common electrode of the transistor in this package (1), and consist of conductive plates extending from the center of the input electrode lead (2) and output electrode lead (3) to both sides, respectively. The common electrode lead (6) is an input electrode bias terminal, CI, which is connected to the input electrode of the transistor via the bias circuit in this package (1).
) is an output electrode bias terminal connected to the output electrode of the transistor via a bias circuit in the package (1).
しかしながら、従来の高周波トランジスタでは(4)バ
イアス端子が1個であるため、回路に流し得る電流が制
限される。(B)装置に組み込む場合、電源供給ライン
がバイアス端子の出ている方向と逆の方向にあった場合
、入力電極リードや出力電極リードをまたいで結線しな
ければならず、高周波回路に悪影響を及ぼしたシ、信頼
性を悪化させる可能性があるなどの欠点があった。However, since the conventional high-frequency transistor (4) has only one bias terminal, the current that can flow through the circuit is limited. (B) When incorporating into a device, if the power supply line is in the opposite direction to the direction in which the bias terminal comes out, it must be connected across the input electrode lead and output electrode lead, which will have a negative impact on the high frequency circuit. However, there were disadvantages such as the possibility of deterioration of reliability.
したがって、との発明の目的は回路に流し得る電流容量
を増大し、作業性、高周波特性および信頼性を良好にす
ることができるバイアス回路およびバイアス端子付き高
周波トランジスタを提供するものである。Therefore, an object of the invention is to provide a bias circuit and a high frequency transistor with a bias terminal, which can increase the current capacity that can flow through the circuit and improve workability, high frequency characteristics, and reliability.
このような目的を達成するため、この発明は入力電極用
バイアス端子および出力電極用バイアス端子の両方また
は一方をパッケージの両側面に配置するものであシ、以
下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention disposes both or one of the input electrode bias terminal and the output electrode bias terminal on both sides of the package, and will be described in detail below using examples. .
第2図はこの発明に係る高周波トランジスタの一実施例
を示す平面図である。同図において、(8a)および(
8b)は前記パッケージ(1)の両側部にそれぞれ設け
た入力電極用バイアス端子、(9m)および(9b)は
前記パッケージ(1)の両側部にそれぞれ設けた出力電
極用バイアス端子である。FIG. 2 is a plan view showing an embodiment of a high frequency transistor according to the present invention. In the figure, (8a) and (
8b) are input electrode bias terminals provided on both sides of the package (1), and (9m) and (9b) are output electrode bias terminals provided on both sides of the package (1).
この構成によるバイアス回路およびバイアス端子付き高
周波トランジスタではパッケージ(1)の両側部にそれ
ぞれ入力電極用バイアス端子および出力電極用バイアス
端子を設けたので、(C)各バイアス端子を並列に使用
することにより、回路に流して得られる電流容量が2倍
になる。の)装置に組み込む場合、一方のバイアス端子
分の電流容量で充分であれば電源供給ラインが2つのバ
イアス端子の出ているどちらの方向にあっても、その方
向の端子に結線すればよいから、入力電極リードや出力
電極リードをまたぐ必要がなく、高周波回路に悪影響を
及ぼしたり、信頼性を悪化させたりする可能性をなくす
ととができる。In the bias circuit and the high-frequency transistor with bias terminals having this configuration, the input electrode bias terminal and the output electrode bias terminal are respectively provided on both sides of the package (1). , the current capacity obtained by flowing it through the circuit doubles. () If the current capacity for one bias terminal is sufficient, you can connect the power supply line to the terminal in that direction, regardless of which direction the two bias terminals are protruding from. There is no need to straddle the input electrode lead or the output electrode lead, and the possibility of adversely affecting the high frequency circuit or deteriorating reliability can be eliminated.
なお、以上の実施例ではバイアス回路およびバイアス端
子付き高周波トランジスタについて説明したが、これに
限定することはなく、例えばパッケージ内部に整合回路
を包含した内部整合形高周波トランジスタについても同
様にできることはもちろんである。Although the above embodiments have been described with respect to a bias circuit and a high-frequency transistor with a bias terminal, the present invention is not limited to this, and it goes without saying that the same can be applied to an internally matched high-frequency transistor that includes a matching circuit inside the package. be.
以上詳細に説明したように、この発明に係る高周波トラ
ンジスタによればパッケージの両側面にバイアス供給端
子を2個づつ設けたので、電流容量を増大させることが
できるうえ、高周波特性および信頼性を向上させること
ができるなどの効果がある。As explained in detail above, according to the high frequency transistor according to the present invention, two bias supply terminals are provided on both sides of the package, so the current capacity can be increased, and the high frequency characteristics and reliability are improved. There are effects such as being able to
第1図は従来の高周波トランジスタを示す平面図、第2
図はこの発明に係る高周波トランジスタの一実施例を示
す平面図である。
(1)・・・拳パッケージ、C2)・・・・入力電極リ
ード、(3)・・・・出力電極リード、(4)および(
5)・―・・共通電極リード、(6)・・・・入力電極
用バイアス端子、σ)・・・拳出力電極用バイアス端子
、(8a)および(8b)・・・・入力電極用バイアス
端子、(9a)および(9b)・・・・出力電極用バイ
アス端子。
なお、図中、同一符号は同一または相当部分を示す。
代理人 葛 野 信 −
第1図
第2図
手続補正書(自発)
58223
昭和 年 月 「1
、発明の名称
高周波トランジスタ
3、補正をする者
代表者片山仁へ部
5、補正の対象
明細書の発明の詳細な説明の欄
6、補正の内容
明細書第2頁第2行の「導電板」を「導体板」と補正す
る。
以 上Figure 1 is a plan view showing a conventional high frequency transistor;
The figure is a plan view showing one embodiment of a high frequency transistor according to the present invention. (1)...Fist package, C2)...Input electrode lead, (3)...Output electrode lead, (4) and (
5)...Common electrode lead, (6)...Bias terminal for input electrode, σ)...Bias terminal for fist output electrode, (8a) and (8b)...Bias for input electrode Terminals (9a) and (9b): bias terminals for output electrodes. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1 Figure 2 Procedural amendment (voluntary) 58223 Month, Showa 1. Title of the invention: High-frequency transistor 3. To the representative Hitoshi Katayama of the person making the amendment: 5. In Column 6 of the Detailed Description of the Invention, "conductive plate" in the second line of page 2 of the specification of the contents of the amendment is amended to read "conductive plate". that's all
Claims (1)
極用バイアス回路を包含し、前記ノくツケージ外面に入
力電極用バイアス端子および出力電極用バイアス端子を
設けた高周波トランジスタにおいて、前記入力電極用バ
イアス端子および前記出力電極用バイアス端子の両方ま
たは一方を前記パッケージの両側部に配置したことを特
徴とする高周波トランジスタ。In a high-frequency transistor including an input electrode bias circuit and an output electrode bias circuit inside a package, and an input electrode bias terminal and an output electrode bias terminal provided on the outer surface of the cage, the input electrode bias terminal and the A high-frequency transistor characterized in that both or one of output electrode bias terminals are arranged on both sides of the package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18500482A JPS5972752A (en) | 1982-10-19 | 1982-10-19 | High frequency transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18500482A JPS5972752A (en) | 1982-10-19 | 1982-10-19 | High frequency transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5972752A true JPS5972752A (en) | 1984-04-24 |
Family
ID=16163089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18500482A Pending JPS5972752A (en) | 1982-10-19 | 1982-10-19 | High frequency transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5972752A (en) |
-
1982
- 1982-10-19 JP JP18500482A patent/JPS5972752A/en active Pending
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