JPS5972695A - 半導体メモリ装置 - Google Patents
半導体メモリ装置Info
- Publication number
- JPS5972695A JPS5972695A JP57184361A JP18436182A JPS5972695A JP S5972695 A JPS5972695 A JP S5972695A JP 57184361 A JP57184361 A JP 57184361A JP 18436182 A JP18436182 A JP 18436182A JP S5972695 A JPS5972695 A JP S5972695A
- Authority
- JP
- Japan
- Prior art keywords
- address signal
- memory cell
- column
- row
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57184361A JPS5972695A (ja) | 1982-10-18 | 1982-10-18 | 半導体メモリ装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57184361A JPS5972695A (ja) | 1982-10-18 | 1982-10-18 | 半導体メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5972695A true JPS5972695A (ja) | 1984-04-24 |
JPS638556B2 JPS638556B2 (US20090163788A1-20090625-C00002.png) | 1988-02-23 |
Family
ID=16151890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57184361A Granted JPS5972695A (ja) | 1982-10-18 | 1982-10-18 | 半導体メモリ装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5972695A (US20090163788A1-20090625-C00002.png) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61126689A (ja) * | 1984-11-21 | 1986-06-14 | Fujitsu Ltd | 半導体記憶装置 |
JPS63227125A (ja) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | デコーダ用組み合わせ論理回路 |
JPH01245489A (ja) * | 1988-03-25 | 1989-09-29 | Hitachi Ltd | 半導体記憶装置 |
JPH02158995A (ja) * | 1988-12-09 | 1990-06-19 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US6714478B2 (en) | 2002-02-21 | 2004-03-30 | Renesas Technology Corp. | Semiconductor memory device having divided word line structure |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0225150U (US20090163788A1-20090625-C00002.png) * | 1988-08-06 | 1990-02-19 |
-
1982
- 1982-10-18 JP JP57184361A patent/JPS5972695A/ja active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61126689A (ja) * | 1984-11-21 | 1986-06-14 | Fujitsu Ltd | 半導体記憶装置 |
JPH0467717B2 (US20090163788A1-20090625-C00002.png) * | 1984-11-21 | 1992-10-29 | Fujitsu Ltd | |
JPS63227125A (ja) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | デコーダ用組み合わせ論理回路 |
JPH01245489A (ja) * | 1988-03-25 | 1989-09-29 | Hitachi Ltd | 半導体記憶装置 |
JPH02158995A (ja) * | 1988-12-09 | 1990-06-19 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US6714478B2 (en) | 2002-02-21 | 2004-03-30 | Renesas Technology Corp. | Semiconductor memory device having divided word line structure |
Also Published As
Publication number | Publication date |
---|---|
JPS638556B2 (US20090163788A1-20090625-C00002.png) | 1988-02-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100538883B1 (ko) | 반도체 메모리 장치 | |
US4542486A (en) | Semiconductor memory device | |
US7630230B2 (en) | Static random access memory architecture | |
KR100443029B1 (ko) | 반도체기억장치,반도체장치,데이타처리장치및컴퓨터시스템 | |
KR930001282B1 (ko) | 반도체 메모리 | |
JP2836596B2 (ja) | 連想メモリ | |
JPH05347092A (ja) | Dram、sram組み合わせアレイ | |
US10026468B2 (en) | DRAM with segmented word line switching circuit for causing selection of portion of rows and circuitry for a variable page width control scheme | |
KR0158933B1 (ko) | 반도체 기억 장치 | |
JPS5972695A (ja) | 半導体メモリ装置 | |
JPH0421956B2 (US20090163788A1-20090625-C00002.png) | ||
US6404693B1 (en) | Integrated circuit memory devices that select sub-array blocks and input/output line pairs based on input/output bandwidth, and methods of controlling same | |
US6404695B1 (en) | Semiconductor memory device including a plurality of memory blocks arranged in rows and columns | |
US6426913B1 (en) | Semiconductor memory device and layout method thereof | |
JPS5972698A (ja) | 半導体メモリ装置 | |
JPH11149787A (ja) | 半導体記憶装置 | |
US6219296B1 (en) | Multiport memory cell having a reduced number of write wordlines | |
JPH07114794A (ja) | 半導体記憶装置 | |
JPS6218992B2 (US20090163788A1-20090625-C00002.png) | ||
JP4723711B2 (ja) | 半導体メモリ | |
JPH0413798B2 (US20090163788A1-20090625-C00002.png) | ||
JPH036598B2 (US20090163788A1-20090625-C00002.png) | ||
JPH0421957B2 (US20090163788A1-20090625-C00002.png) | ||
JPS62142347A (ja) | 半導体メモリ装置 | |
JPH0347747B2 (US20090163788A1-20090625-C00002.png) |