JPS5971499U - Erasable read-only memory - Google Patents

Erasable read-only memory

Info

Publication number
JPS5971499U
JPS5971499U JP16612482U JP16612482U JPS5971499U JP S5971499 U JPS5971499 U JP S5971499U JP 16612482 U JP16612482 U JP 16612482U JP 16612482 U JP16612482 U JP 16612482U JP S5971499 U JPS5971499 U JP S5971499U
Authority
JP
Japan
Prior art keywords
memory
erasable read
data
read
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16612482U
Other languages
Japanese (ja)
Other versions
JPS647520Y2 (en
Inventor
石原　富裕
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP16612482U priority Critical patent/JPS5971499U/en
Publication of JPS5971499U publication Critical patent/JPS5971499U/en
Application granted granted Critical
Publication of JPS647520Y2 publication Critical patent/JPS647520Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロック図である。 １．２・・・・・・シフト−レジスタ、３・・・・・・
ラッチ、４・・・・・・メモリ、５・・・・・・シフト
・データ、６・・・・・・シフト・クロック、７・・・
・・・ラッチ・ストローブ、８・・・・・・アウト・エ
ネーブル、９・・・・・・アンド・ゲート、１０・・・
・・・トライステート・バッファ。FIG. 1 is a block diagram showing one embodiment of the present invention. 1.2...Shift-register, 3...
Latch, 4...Memory, 5...Shift data, 6...Shift clock, 7...
...Latch strobe, 8...Out enable, 9...And gate, 10...
...tri-state buffer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データを記憶する位置を示すアドレス部と、記憶されて
いるデータの内容を読み出すデータ部がシフトレジスタ
で構成されることを特徴とする消去可能な読み出し専用
メモリ。An erasable read-only memory characterized in that an address section indicating a position where data is stored and a data section from which the contents of the stored data are read are constituted by a shift register.
JP16612482U 1982-11-01 1982-11-01 Erasable read-only memory Granted JPS5971499U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16612482U JPS5971499U (en) 1982-11-01 1982-11-01 Erasable read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16612482U JPS5971499U (en) 1982-11-01 1982-11-01 Erasable read-only memory

Publications (2)

Publication Number Publication Date
JPS5971499U true JPS5971499U (en) 1984-05-15
JPS647520Y2 JPS647520Y2 (en) 1989-02-28

Family

ID=30363771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16612482U Granted JPS5971499U (en) 1982-11-01 1982-11-01 Erasable read-only memory

Country Status (1)

Country Link
JP (1) JPS5971499U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52122438A (en) * 1976-04-07 1977-10-14 Sanyo Electric Co Ltd Write-in and read-out system
JPS5314525A (en) * 1976-07-26 1978-02-09 Nec Corp Memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52122438A (en) * 1976-04-07 1977-10-14 Sanyo Electric Co Ltd Write-in and read-out system
JPS5314525A (en) * 1976-07-26 1978-02-09 Nec Corp Memory circuit

Also Published As

Publication number Publication date
JPS647520Y2 (en) 1989-02-28

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