JPS59703A - Sequence control system - Google Patents

Abstract

PURPOSE:To control a device to be controlled with a microprocessor, by providing a simple hardware to the microprocessor in controlling sequentially various devices to be controlled, for attaining the instantaneous response within several tens of musec. CONSTITUTION:Sequence information to control sequentially the device to be controlled 2 with the program control of the microprocessor 1 is set to sequence control registers 41-4n via a data bus 7. When the 1st sequence control information (a) is transmitted to the device to be controlled 2 and its response information (b) is applied to a sequence control section 3, the 2nd sequence control information (c) is transmitted to the device to be controlled 2 from a sequence control information register 42 with a control signal (i). When the final sequence control information (g) is transmitted and its response information (h) is transmitted similarly, an interruption control circuit 5 transmits the interrupting signal (g) to the microprocessor 1 for completing a series of control.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a sequence control system for sequentially controlling a controlled bag (1) by means of a microprocessor 9' with immediate response.

Prior Art and Problems When a microprocessor sequentially controls various controlled devices, an interrupt is sent to the microprocessor based on response information from the controlled device. Since it requires steps such as analysis, response information analysis using a program, and creation of the next sequence control information based on the analysis results, it takes a long time to send the next sequence control information to the controlled device ( However, it cannot be applied when an immediate response (within several +1 Isec) is required.

OBJECTS OF THE INVENTION An object of the present invention is to enable a controlled device to be easily controlled by a microprocessor even in sequential control that requires an immediate response. Examples will be described in detail below.

(2) Embodiment of the invention As shown in FIG. 1, a microphone! :1 When a plurality of controlled devices 2 are sequentially controlled by a processor I, conventionally, as mentioned above, an interrupt is made to the microprocessor I based on response information from the controlled device, and the next sequence control is performed by analyzing the interrupt, etc. Information was to be sent to the controlled device 2. In other words, conventional sequence control was based on software.

On the other hand, the present invention enables immediate response control by adding simple hardware, and FIG. 2 is a block diagram of a main part of an embodiment of the present invention. In the figure, 1 is a microprocessor, 2 is a controlled device, 3 is a sequence control section, 41 to 4n are sequence control information registers, 5 is an interrupt control circuit, 6 is an address bus, and 7 is a data bus. . Sequence control information for sequentially controlling the controlled device 2 is created under the program control of the microprocessor l, and the sequence control information registers 41 to 4n are sequentially designated (3) on the address bus 6, and then sent via the data bus 7. and set the sequence control information.

Upon completion of setting this sequence control information, the first sequence control information (al) written in the sequence control information register 41 is sent to the controlled device 3. In response, response information (bl) from the controlled device 2 is sent to the controlled device 3. is applied to the sequence control unit 3, the second sequence control information (
C) is sent to the controlled device 2. When response information fd+ to this second sequence control information (C1) is added from the controlled device 2 to the sequence control unit 3, the control signal (
The third sequence control information (el) is sent from the sequence control information register 43 by Jl.Response information (") to this third sequence control information (el) is added from the controlled device 2 to the sequence control unit 3. Then, the next sequence control information is sent to the controlled device 2 by the control signal fkl.The nth sequence control information (gl is sent from the last sequence control information register 4n,
When the response information (hl) is sent, (A
) The interrupt control circuit 5 sends an interrupt signal (q
) is sent.

Furthermore, since each sequence control information register 41 to 4n is for sending each sequence completion signal ((2) to (pl) to the interrupt control circuit 5, a sequence monitoring function is provided in the interrupt control circuit 5 and It is possible to monitor whether the control is being performed correctly.By transferring this sequence completion signal tm+ to (ρ) to the microprocessor 1 via the interrupt control circuit 5, The microprocessor 1 can also monitor sequence control.

Upon completion of a series of sequence controls, the interrupt signal fql is sent from the interrupt control circuit 5 to the microprocessor 1, so the microprocessor 1 creates sequence control information through the next program control and stores the sequence control information registers 41 to 4n. , and the above control is repeated.

As described above, since the sequence control information is immediately sent out from the sequence control information register group in response to the response information from the controlled device 2, immediate control of the response side (5) is possible.

Effects of the Invention As explained above, the present invention sets sequence control information created under program control of the microprocessor 1 in a sequence control information register group, and transfers sequence control information from the sequence control information register group to a controlled device. 2, and by receiving the response information from the controlled device W2, the next sequence control information is repeatedly sent from the sequence control information register group, and the last sequence control information is sent, and the response is received. When information is received, an interrupt signal is sent to the microprocessor l, and the microprocessor l immediately sends the next sequence control information in response to the response information without performing processing such as interrupt analysis for each sequence. This has the advantage that immediate response control is possible with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of microprocessor therapy and a controlled device, and FIG. 2 is a diagram showing the main parts of the embodiment of the present invention (6). 2 is a microprocessor, 2 is a controlled device, 3 is a sequence control section, 41 to 4n are sequence control information registers, 5 is an interrupt control circuit, 6 is an address bus, and 7 is a data bus. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Gobe Tamamushi and 3 others (7)

Claims (1)

[Claims] In a system in which a controlled device is sequentially controlled by a microprocessor, a sequence control unit consisting of a sequence control information register group and an interrupt control circuit is provided, and sequence control information created under program control of the microprocessor is controlled by the sequence control unit. When the controlled device sends response information to the sequence control information to the sequence control unit, the sequence control unit transfers the next sequence control information from the sequence control information register group to the sequence control information register group. A sequence control system characterized in that the interrupt signal is sent to a controlled device, and upon completion of a predetermined sequence control, the interrupt control circuit sends an interrupt signal to the microprocessor.