JPH0512171A - Peripheral controller - Google Patents

Abstract

PURPOSE:To obtain a peripheral controller which can delay the transfer of a command by an optional time and can evaluate the command overrun, etc., with high efficiency. CONSTITUTION:A peripheral controller 1 consists of a command transfer circuit 2 which controls the transfer of commands among plural peripheral devices 11, a microporgram control circuit 3 which is connected to a CPU 12 to receive various control instructions and controls each device included in the controller 1, and a command transfer delay counter 4 which receives a command transfer delay command produced by the CPU 12 via the circuit 3 to set the value to a counter and delays the command transfer speed by an optional time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral controller, and more particularly to a peripheral controller having a function of controlling command transfer delay.

[0002]

2. Description of the Related Art A conventional peripheral control device, when performing a command overrun test, puts a high load on the peripheral device so as to intentionally generate a command overrun, or makes a routine for delaying command transfer by firmware and evaluates it. Was there.

[0003]

In the above-mentioned conventional peripheral control device, in order to intentionally generate a command overrun, a high load is applied to the peripheral device, or a routine for delaying command transfer is made in firmware. So
There is a problem that a lot of manpower is required for preparation and a long test time is required for conducting a test such as command overrun.

An object of the present invention is to provide a peripheral control device capable of delaying command transfer by an arbitrary time and efficiently evaluating command overrun and the like.

[0005]

SUMMARY OF THE INVENTION A peripheral control device of the present invention is a central processing unit and a command transfer circuit which is connected to a plurality of peripheral devices and controls command transfer between the plurality of peripheral devices and the central processing unit. In a peripheral control device having a micro program control circuit connected to a device and receiving various control instructions to control the command transfer circuit, a command transfer delay instruction command issued by the central processing unit is passed through the micro program control circuit. The configuration is such that a command transfer delay counter that sets a value in the reception counter and delays the command transfer speed for an arbitrary time is provided.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The peripheral control device 1 of the present invention is connected to a command transfer circuit 2 for controlling command transfer between a plurality of peripheral devices 11 and a central processing unit 12, and receives various control instructions to receive the peripheral control device 1. The command transfer delay instruction command issued by the central processing unit 12 and the micro program control circuit 3 for controlling each device therein are set in the receiving counter via the micro program control circuit 3 to delay the command transfer speed by an arbitrary time. It is composed of the command transfer delay counter 4.

Next, the operation will be described.

Upon receiving the command execution instruction from the central processing unit 12 to the peripheral device 11, the micro program control circuit 3 sets a command in the command transfer circuit 2, and the command transfer circuit 2 communicates with the peripheral device 11. Perform command transfer. Upon receiving the command transfer delay instruction command from the central processing unit 12, the microprogram control circuit 3 sets the delay time indicated by the received command transfer delay instruction command in the command transfer delay counter 4. After that, when the micro program control circuit 3 receives a command transfer instruction for the peripheral device 11 from the central processing unit 12, it sets a command and a transfer direction in the command transfer circuit 2 and then sends a delay start signal to the command transfer delay counter 4. send. When the command transfer delay counter 4 receives the delay start signal from the microprogram control circuit 3,
When the counter is started and the number of counters set in advance is exhausted,
A transfer start signal is sent to the command transfer circuit 2. Upon receiving the transfer start signal from the command transfer delay counter 4, the command transfer circuit 2 transfers the command to the peripheral device 11 according to the previously set command and transfer direction.

[0011]

As described above, according to the present invention, the command transfer delay instruction command issued by the central processing unit is received through the micro program control circuit, the value is set in the counter, and the command transfer speed is delayed for an arbitrary time. By providing the command transfer delay counter, command transfer can be delayed by an arbitrary time, and there is an effect that the command overrun and the like can be efficiently evaluated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Peripheral Control Device 2 Command Transfer Circuit 3 Micro Program Control Circuit 4 Command Transfer Delay Counter 11 Peripheral Device 12 Central Processing Unit

Claims (1)

Claim: What is claimed is: 1. A command transfer circuit connected to a central processing unit and a plurality of peripheral devices to control command transfer between the plurality of peripheral devices, and a variety of devices connected to the central processing unit. In a peripheral control device having a micro program control circuit for receiving a control instruction and controlling the command transfer circuit, a command transfer delay instruction command issued by the central processing unit is set in a reception counter via the micro program control circuit. A peripheral control device is provided with a command transfer delay counter that delays the command transfer speed for an arbitrary time.