JPH02227758A - Peripheral controller - Google Patents

Abstract

PURPOSE:To evaluate a command overrun, etc., with high efficiency by providing a command transfer delay counter to delay the transfer of an instruction command produced by a CPU. CONSTITUTION:A microprogram control circuit 13 receives a command transfer instruction command from a CPU via a line 15. Hereafter a command is set to a command transfer circuit 12 via a line 17 and a signal is sent to a command transfer delay counter 14 via a line 18 when an executing instruction is received from the CPU to a peripheral device. The counter 14 receives the signal from the circuit 13 and starts to send a signal to the circuit 12 via a line 16 at the set time of the counter 14. Thus the circuit 12 transfers a command to the peripheral device based on the command already set and the transfer direction. Thus the circuit 13 controls a peripheral controller 11 and therefore a command overrun, etc., can be evaluated with high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a peripheral control device that controls a plurality of peripheral devices, and in particular, has a built-in command transfer delay circuit and issues a command transfer delay instruction command from a central processing unit. The present invention relates to an apparatus capable of controlling command transfer delay.

2. Description of the Related Art In conventional devices, a high load is placed on a peripheral device, resulting in a delay in transfer speed, but a peripheral control device with a built-in command transfer delay circuit has not been known.

For this reason, either a high load is placed on peripheral devices to intentionally cause command overruns, etc., or firmware (F.
W) and created a routine to delay command transfer and evaluated it.

Problems to be Solved by the Invention With the conventional peripheral control devices mentioned above, the only way to intentionally cause command overruns is to place a high load on the peripheral device or create a routine in firmware (FW) that delays command transfer. This required a lot of manpower. Therefore, a long test time was required to test command overruns and the like.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel peripheral control device that eliminates the above-mentioned drawbacks inherent in the conventional technology and makes it possible to efficiently evaluate command overruns and the like.

Means for Solving the Problems In order to achieve the above object, a peripheral control device with a built-in command transfer delay circuit according to the present invention is provided with a counter in which a command transfer delay time is set, and a central processing unit is provided with a counter to which a command transfer delay time is set. The configuration is such that the transfer of the command after issuing the instruction command is delayed by a time proportional to the value set in the above-mentioned counter, and by doing so, the central processing unit is It becomes possible to easily evaluate command overruns and the like simply by issuing a command transfer delay instruction command.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a peripheral control device 11 according to the present invention includes a command transfer circuit 12 and a microprogram control circuit 1.
3, and a command transfer delay counter 14 in which a command transfer delay time is set.

Normally, when the microprogram control circuit 13 receives a command execution instruction from a central processing unit (not shown) to a peripheral device (not shown) through a line 15, the microprogram control circuit 13 transfers the command to the peripheral device through a line 17 via a command transfer circuit 12. Transfer commands. The microprogram control circuit 13 receives and receives command transfer delay instruction commands from the central processing unit through the line 15, and thereafter the microprogram control circuit 1
3 receives an execution instruction from the central processing unit to the peripheral device through the line 15, and then sends it to the command transfer circuit 1 through the line 17.
2 to set the command and transfer direction, and send a signal to the command transfer delay counter 14 through line 18. The command transfer delay counter 14 is connected to the microprogram control circuit 1.
When the signal from 3 is received, the counter is started and when the number of counters set in the counter is exhausted, line 16 is activated.
A signal is sent to the command transfer circuit 12 through the command transfer circuit 12. When the command transfer circuit 12 receives a signal from the command transfer delay counter 14, it transfers the command to the peripheral device using the already set command and transfer direction.

As described in detail, according to the present invention, the central processing unit issues a command transfer delay instruction command, thereby making it possible to delay command transfer and efficiently evaluating command overruns, etc. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Peripheral control device, 12... Command transfer circuit, 13... Microprogram control circuit, 14...
Command Transfer Delay Counter Patent Applicant: NEC Corporation Representative Patent Attorney: Yuta Kumagai

Claims (1)

[Claims] Processing of signals or commands for instructing input/output operations in a command processing system having a central processing unit, a peripheral control device for controlling a plurality of peripheral devices, and a communication bus for transferring information between the devices. In a peripheral control device that logically has a plurality of channels for processing operations and command transfer of peripheral devices, a command transfer circuit that controls command transfer between the central processing unit, the peripheral control device, and the peripheral devices; A peripheral characterized by having a microprogram control circuit for controlling the inside of the control device, and a command transfer delay counter capable of slowing down the command transfer speed by the central processing unit issuing a command transfer delay instruction command. Control device.