JP2747153B2 - Response signal distribution method - Google Patents
Response signal distribution methodInfo
- Publication number
- JP2747153B2 JP2747153B2 JP2305692A JP2305692A JP2747153B2 JP 2747153 B2 JP2747153 B2 JP 2747153B2 JP 2305692 A JP2305692 A JP 2305692A JP 2305692 A JP2305692 A JP 2305692A JP 2747153 B2 JP2747153 B2 JP 2747153B2
- Authority
- JP
- Japan
- Prior art keywords
- response signal
- unit
- connection flag
- signal distribution
- wait
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【0001】[0001]
【産業上の利用分野】本発明は、応答信号振分方式に関
し、特に情報処理システムにおける応答信号振分方式に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a response signal distribution method, and more particularly, to a response signal distribution method in an information processing system.
【0002】[0002]
【従来の技術】通常、応答信号振分方式は、情報処理シ
ステムの基本ソフトで使用されており、最小限のロジッ
クで、高性能と機能が要求される。2. Description of the Related Art In general, a response signal distribution system is used in basic software of an information processing system, and requires high performance and functions with minimum logic.
【0003】従来の応答信号振分方式では、図2に示す
ように、応答信号値の異なる装置4と装置5の制御を、
制御部3で装置4,装置5に要求し、装置4,装置5か
らの応答信号を応答信号振分部6により、応答信号待ち
指定部7と装置4の応答信号解析部8,装置5の応答信
号解析部9と応答信号待ち指定解除部10に制御を渡し
処理を行う。このように、応答信号振分部においては、
応答信号のみを用いて、応答信号待ち指定部と応答信号
解析部と応答信号待ち指定解除部を必ず実行することに
より、装置を制御する。In the conventional response signal distribution method, as shown in FIG. 2, control of the devices 4 and 5 having different response signal values is performed by:
The control unit 3 requests the devices 4 and 5 and the response signals from the devices 4 and 5 are transmitted by the response signal distribution unit 6 to the response signal wait designation unit 7 and the response signal analysis unit 8 of the device 4 and the response signal analysis unit 8 of the device 4. The control is passed to the response signal analysis unit 9 and the response signal wait designation release unit 10 for processing. Thus, in the response signal distribution unit,
The apparatus is controlled by using only the response signal and always executing the response signal wait designation unit, the response signal analysis unit, and the response signal wait designation release unit.
【0004】[0004]
【発明が解決しようとする課題】従来の応答信号振分方
式では、応答信号振分時の判断材料として応答信号しか
用いない為、判断方法の複雑化により装置制御処理速度
が低下するという欠点がある。In the conventional response signal distribution method, only the response signal is used as a judgment material at the time of response signal distribution. is there.
【0005】本発明の目的は、以上の欠点を解決し、応
答信号振分の処理速度を向上し、装置制御処理速度を向
上可能とする応答信号振分方式を提供することにある。An object of the present invention is to provide a response signal distribution method which solves the above-mentioned drawbacks, improves the processing speed of response signal distribution, and can improve the processing speed of device control.
【0006】[0006]
【課題を解決するための手段】本発明の応答信号振分方
式は、応答信号の値が異なる補助記憶装置を同時に制御
する情報処理システムにおいて、接続フラグを設定する
接続フラグ設定部と、接続フラグ設定部に接続され複数
個の装置を制御する制御部と、接続フラグの状態判断
と、応答信号の異なる装置が複数接続かを判断する応答
信号振分部と、前記装置が複数接続の場合は応答信号待
ちを指定し実行する応答信号待ち指定部と、応答信号の
解析処理を行う応答信号解析部と、応答信号待ち指定解
除部とを有している。According to the present invention, there is provided a response signal distribution system, comprising: a connection flag setting unit for setting a connection flag in an information processing system for simultaneously controlling auxiliary storage devices having different response signal values; A control unit that is connected to the setting unit and controls a plurality of devices; a connection flag state determination; a response signal distribution unit that determines whether a device having a different response signal is a multiple connection; and It has a response signal wait designation unit that designates and executes a response signal wait, a response signal analysis unit that performs response signal analysis processing, and a response signal wait designation release unit.
【0007】[0007]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0008】図1は、本発明の一実施例の構成図であ
る。図1において、本発明の一実施例は応答信号値の異
なる装置4と装置5の制御を、接続フラグ設定部1で接
続フラグ2を設定し、制御部3で装置4,装置5に要求
し、装置4,装置5からの応答信号を応答信号振分部6
により、応答信号待ち指定部7と装置4の応答信号解析
部8,装置5の応答信号解析部9と応答信号待ち指定解
除部10に制御を渡し処理を行う。FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, one embodiment of the present invention requests the control of the devices 4 and 5 having different response signal values by setting the connection flag 2 by the connection flag setting unit 1 and requesting the control of the devices 4 and 5 by the control unit 3. The response signals from the devices 4 and 5 to the response signal distribution unit 6
Thus, control is passed to the response signal wait designation unit 7, the response signal analysis unit 8 of the device 4, the response signal analysis unit 9 of the device 5, and the response signal wait designation release unit 10, and the process is performed.
【0009】図3は、応答信号値の格納領域の説明図で
ある。図3において、応答信号値の格納領域11は、応
答信号の異なる各位置に、各応答信号領域が対応し、装
置が、応答信号振分部に応答信号を通知すると、応答信
号領域の状態が0から1に変化する。FIG. 3 is an explanatory diagram of a storage area for response signal values. In FIG. 3, the response signal value storage area 11 corresponds to each of the different positions of the response signal, and when the device notifies the response signal distribution unit of the response signal, the state of the response signal area is changed. It changes from 0 to 1.
【0010】図4は、接続フラグの説明図である。図4
において、接続フラグ12は、応答信号の異なる各装置
に、各接続フラグ領域が対応し、各装置が制御可能な場
合、各接続フラグ領域の状態を0から1とする。FIG. 4 is an explanatory diagram of the connection flag. FIG.
In the connection flag 12, each connection flag area corresponds to each device having a different response signal, and when each device can be controlled, the state of each connection flag region is changed from 0 to 1.
【0011】図5は、応答信号待ち指定の格納領域の説
明図である。図5において、応答信号待ち指定の格納領
域13は、応答信号の異なる各装置に、各待ち指定領域
が対応し、ある装置の応答信号に対する処理を実行中に
他の装置からの応答信号を保留にするため、各待ち指定
領域の状態を0から1とする。FIG. 5 is an explanatory diagram of a storage area designated for waiting for a response signal. In FIG. 5, a response signal wait designation storage area 13 has a wait designation area corresponding to each device having a different response signal, and holds a response signal from another device while executing a process for a response signal of a certain device. Therefore, the state of each designated wait area is changed from 0 to 1.
【0012】図6は、接続フラグ設定部の処理の流れ図
である。図6において、装置に対する応答信号値の判断
14,応答信号値に対する接続フラグ設定15により、
接続フラグ12を設定する。FIG. 6 is a flowchart of the processing of the connection flag setting unit. In FIG. 6, a determination 14 of a response signal value for the device and a connection flag setting 15 for the response signal value
The connection flag 12 is set.
【0013】図7は、応答信号振分部の処理の流れ図で
ある。図7において、接続フラグの状態判断16を行
い、応答信号の異なる装置が複数接続かの判断17によ
り、複数接続の場合は、応答信号格納領域と接続フラグ
より待ち指定格納領域設定値を算出18と応答信号待ち
指定部7の処理19を実施後、応答信号解析部の処理2
0と応答信号待ち指定解除部の処理22を行い、複数接
続でない場合は、応答信号解析部8,9の処理20を行
い、装置の制御を終了する。FIG. 7 is a flowchart of the processing of the response signal distribution unit. In FIG. 7, a connection flag state determination 16 is performed, and if a plurality of devices having different response signals are determined to be a plurality of connections 17, in the case of a plurality of connections, a wait designation storage area setting value is calculated from the response signal storage area and the connection flag 18 And the processing 19 of the response signal waiting designating section 7, and then the processing 2 of the response signal analyzing section.
If 0 and the process 22 of the response signal wait designation canceling unit are performed, and if there is not a plurality of connections, the process 20 of the response signal analyzing units 8 and 9 is performed and the control of the device is ended.
【0014】次に、応答信号値が0から7までの装置制
御が可能である本発明のシステムにおいて、まず、応答
信号値が1である装置5を接続し、装置5を制御する場
合の本発明の実施例について説明する。Next, in the system according to the present invention capable of controlling the response signal value from 0 to 7, first, the device 5 in which the response signal value is 1 is connected, An embodiment of the present invention will be described.
【0015】本システムが起動されると接続フラグ設定
部1により、接続フラグ2を設定する。接続フラグ設定
部1では、装置に対する応答信号値の判断14により、
装置5の応答信号値が1であると確定し、応答信号値に
対する接続フラグ設定15により、接続フラグ12の信
号値1領域の状態を0から1とする。この接続フラグ設
定部1の処理により、本システムの動作準備が完了す
る。When the present system is started, a connection flag 2 is set by the connection flag setting unit 1. The connection flag setting unit 1 determines the response signal value 14 for the device,
It is determined that the response signal value of the device 5 is 1, and the state of the signal value 1 area of the connection flag 12 is changed from 0 to 1 by the connection flag setting 15 for the response signal value. By the processing of the connection flag setting unit 1, the operation preparation of the present system is completed.
【0016】次に、制御部3より装置5に命令すると、
装置5から応答信号により応答信号振分部6が起動す
る。応答信号振分部6では、接続フラグの状態判断16
により、接続フラグ12を参照し、応答信号の異なる装
置が複数接続かの判断17により、装置5のみ接続され
ている状態であると判断し、応答信号解析部の処理21
により、装置5の応答信号解析部9を実施し、装置の制
御を終了する。Next, when the control unit 3 instructs the device 5,
The response signal distribution unit 6 is activated by the response signal from the device 5. In the response signal distribution unit 6, the connection flag state determination 16
With reference to the connection flag 12, it is determined that only the device 5 is connected according to the determination 17 as to whether a plurality of devices having different response signals are connected, and the processing 21 of the response signal analysis unit is performed.
As a result, the response signal analysis unit 9 of the device 5 is executed, and the control of the device ends.
【0017】次に、応答信号値が0から7までの装置制
御が可能である本発明のシステムにおいて、応答信号値
が各々0,1である装置4,装置5を接続し、装置5を
制御する場合の本発明の実施例について説明する。Next, in the system according to the present invention in which the response signal value can be controlled from 0 to 7, the devices 4 and 5 whose response signal values are 0 and 1 are connected, and the device 5 is controlled. An embodiment of the present invention will be described.
【0018】本システムが起動されると接続フラグ設定
部1により、接続フラグ2を設定する。接続フラグ設定
部1では、装置に対する応答信号値の判断14により、
装置4と装置5の応答信号値が各々0,1であると確定
し、応答信号値に対する接続フラグ設定15により、接
続フラグ12の信号値0領域,信号値1領域の状態を0
から1とする。この接続フラグ設定部1の処理により、
本システムの動作準備が完了する。When the system is started, the connection flag setting unit 1 sets a connection flag 2. The connection flag setting unit 1 determines the response signal value 14 for the device,
It is determined that the response signal values of the device 4 and the device 5 are 0 and 1, respectively, and the connection flag setting 15 for the response signal value changes the state of the signal value 0 region and the signal value 1 region of the connection flag 12 to 0.
From 1. By the processing of the connection flag setting unit 1,
The operation preparation of this system is completed.
【0019】次に、制御部3より装置5に命令すると、
装置5から応答信号により応答信号振分部6が起動す
る。応答信号振分部6では、接続フラグの状態判断16
により、接続フラグ12を参照し、応答信号の異なる装
置が複数接続かの判断17により、応答信号格納領域と
接続フラグより待ち指定格納領域設定値を算出18と応
答信号持ち指定部7の処理19により、応答信号待ち指
定格納領域13の信号値0領域の状態を0から1とし、
応答信号解析部9の処理20により、装置5の応答信号
解析部9を実施し、応答信号持ち指定解除部9の処理2
2により、応答信号待ち指定格納領域11の信号値0領
域の状態を1から0とし、装置の制御を終了する。Next, when the controller 3 instructs the device 5,
The response signal distribution unit 6 is activated by the response signal from the device 5. In the response signal distribution unit 6, the connection flag state determination 16
By referring to the connection flag 12 and determining whether a plurality of devices having different response signals are connected to each other, a wait designation storage area setting value is calculated from the response signal storage area and the connection flag 18 and a process 19 of the response signal holding designation unit 7 is performed 19 As a result, the state of the signal value 0 area of the response signal wait designation storage area 13 is changed from 0 to 1,
The response signal analysis unit 9 of the device 5 is executed by the process 20 of the response signal analysis unit 9, and the process 2 of the response signal holding designation release unit 9 is performed.
According to 2, the state of the signal value 0 area of the response signal wait designation storage area 11 is changed from 1 to 0, and the control of the apparatus is ended.
【0020】[0020]
【発明の効果】以上の説明から明らかなごとく、本発明
の応答信号振分方式によれば、応答信号値が同一の補助
記憶装置のみ接続されているシステムにおいて、装置制
御処理速度が向上する効果を得ることができる。As is clear from the above description, according to the response signal distribution method of the present invention, in a system in which only auxiliary storage devices having the same response signal value are connected, the device control processing speed is improved. Can be obtained.
【図1】本発明の一実施例の構成を示す図である。FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.
【図2】従来の応答信号振分方式の一例の構成を示す図
である。FIG. 2 is a diagram showing a configuration of an example of a conventional response signal distribution system.
【図3】応答信号値の格納領域の説明図である。FIG. 3 is an explanatory diagram of a storage area of a response signal value.
【図4】接続フラグの説明図である。FIG. 4 is an explanatory diagram of a connection flag.
【図5】応答信号待ち指定の格納領域の説明図である。FIG. 5 is an explanatory diagram of a storage area for response signal wait designation;
【図6】接続フラグ設定部の処理の流れを示す図であ
る。FIG. 6 is a diagram showing a processing flow of a connection flag setting unit.
【図7】応答信号振分部の処理の流れを示す図である。FIG. 7 is a diagram showing a flow of processing of a response signal distribution unit.
1 接続フラグ設定部 2 接続フラグ 3 制御部 4 装置 5 装置 6 応答信号振分部 7 応答信号ち指定部 8 応答信号解析部 9 応答信号解析部 10 応答信号待ち指定解除部 REFERENCE SIGNS LIST 1 connection flag setting unit 2 connection flag 3 control unit 4 device 5 device 6 response signal distribution unit 7 response signal designation unit 8 response signal analysis unit 9 response signal analysis unit 10 response signal wait designation release unit
Claims (1)
時に制御する情報処理システムにおいて、接続フラグを
設定する接続フラグ設定部と、接続フラグ設定部に接続
され複数個の装置を制御する制御部と、接続フラグの状
態判断と、応答信号の異なる装置が複数接続かを判断す
る応答信号振分部と、前記装置が複数接続の場合は応答
信号待ちを指定し実行する応答信号待ち指定部と、応答
信号の解析処理を行う応答信号解析部と、応答信号待ち
指定解除部とを有し、接続装置について接続フラグを接
続フラグ設定部により設定後、制御部で命令した装置か
らの応答信号に対して、応答信号振分部で接続フラグと
応答信号値により、応答信号待ち指定部と装置に対する
応答信号解析部と応答信号待ち指定解除部を用いて処理
を行うことを特徴とする応答信号振分方式。1. An information processing system for simultaneously controlling auxiliary storage devices having different response signal values, a connection flag setting unit for setting a connection flag, and a control unit connected to the connection flag setting unit for controlling a plurality of devices. A connection flag state determination, a response signal distribution unit that determines whether a device having a different response signal is a plurality of connections, and a response signal wait designation unit that specifies and executes a response signal wait when the device has a plurality of connections. A response signal analysis unit that performs a response signal analysis process, and a response signal wait designation release unit. After setting a connection flag for the connected device by the connection flag setting unit, the response signal from the device instructed by the control unit is output. On the other hand, according to the connection flag and the response signal value in the response signal distribution unit, processing is performed using a response signal wait designation unit, a response signal analysis unit for the device, and a response signal wait designation release unit. Response signal distribution method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2305692A JP2747153B2 (en) | 1992-02-10 | 1992-02-10 | Response signal distribution method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2305692A JP2747153B2 (en) | 1992-02-10 | 1992-02-10 | Response signal distribution method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05225106A JPH05225106A (en) | 1993-09-03 |
JP2747153B2 true JP2747153B2 (en) | 1998-05-06 |
Family
ID=12099788
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JP2305692A Expired - Fee Related JP2747153B2 (en) | 1992-02-10 | 1992-02-10 | Response signal distribution method |
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JP (1) | JP2747153B2 (en) |
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KR100451170B1 (en) * | 2000-09-20 | 2004-10-02 | 엘지전자 주식회사 | Release-guard signal generation circuit for read/write for processor |
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