JPS63186357A - Circuit for setting dma transfer start command - Google Patents

Circuit for setting dma transfer start command

Info

Publication number
JPS63186357A
JPS63186357A JP1890087A JP1890087A JPS63186357A JP S63186357 A JPS63186357 A JP S63186357A JP 1890087 A JP1890087 A JP 1890087A JP 1890087 A JP1890087 A JP 1890087A JP S63186357 A JPS63186357 A JP S63186357A
Authority
JP
Japan
Prior art keywords
dma transfer
dma
transfer
start command
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1890087A
Other languages
Japanese (ja)
Inventor
Atsushi Okada
淳 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1890087A priority Critical patent/JPS63186357A/en
Publication of JPS63186357A publication Critical patent/JPS63186357A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize the continuous DMA transfer at high speed by setting a DMA transfer start command at a DMA controller after the end of the DMA transfer so that a command for the next transfer can be set at the controller during the DMA transfer. CONSTITUTION:A latch 4 holds a DMA transfer start command setting signal 5 and outputs this signal 5 as a DMA transfer start command signal 3 after the end of transfer by a DMA transfer end signal 6 received from a DMA controller 1. The controller 1 works with a parameter setting signal 2 which decides a transfer way and the signal 3. Therefore the signal 5 held by the latch 4 is set as the signal 3 by the signal 6 after the end of transfer. The controller 1 works with the input of both signals 2 and 3 after the end of transfer. Thus a transfer start command is set. In such a way, the continuous DMA transfer is carried out at high speed.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明はＤＭＡコントローラのＤＭＡ転送開始コマンド
設定回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA transfer start command setting circuit for a DMA controller.

［従来の技術］ 従来、ＤＭＡコントローラに対するコマンド設定は、転
送中に次回のパラメータ設定が可能であるＤＭＡコント
ローラにおいても、ＤＭＡ転送開始コマンドだけは設定
できないために、ＤＭＡ転送終了割込を用いてパラメー
タを設定していた。[Prior Art] Conventionally, command setting for a DMA controller is performed using a DMA transfer end interrupt, since even in a DMA controller where it is possible to set the next parameter during transfer, only the DMA transfer start command cannot be set. was set.

［発明が解決しようとする問題点１ 上述した従来のＤＭＡコントローラに対するパラメータ
設定は、ＤＭＡ転送終了後行なわれるため、そのパラメ
ータ設定期間はＤＭＡコントローラは動作することがで
きず、連続ＤＭＡ転送を高速に行なうことが困難であっ
た。[Problem to be Solved by the Invention 1] Since the parameter settings for the conventional DMA controller described above are performed after the completion of DMA transfer, the DMA controller cannot operate during the parameter setting period, and it is difficult to perform continuous DMA transfer at high speed. It was difficult to do.

本発明の目的は連続ＤＭＡ転送を高速に行なうＤＭＡ転
送開始コマンド設定回路を提供することにある。An object of the present invention is to provide a DMA transfer start command setting circuit that performs continuous DMA transfer at high speed.

［問題点を解決するための手段］ 本発明は連続したＤＭＡ転送を行なうシステムにおいて
、ＤＭＡ転送中に次回のＤＭＡ転送コマンドを設定可能
なＤＭＡコントローラと、Ｄ　Ｍ　Ａ転送開始コマンド
をＤＭＡ転送終了後にＤＭＡコントローラに設定するコ
マンド設定回路とを有することを特徴とするＤＭＡ転送
開始コマンド設定回路である。[Means for Solving the Problem] The present invention provides a DMA controller that can set the next DMA transfer command during DMA transfer, and a DMA transfer start command that can be set after the DMA transfer is completed in a system that performs continuous DMA transfer. 1 is a DMA transfer start command setting circuit characterized by comprising a command setting circuit for setting a command to a DMA controller.

［実施例］ 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第１図に示すように、本発明に係るＤＭＡ転送開始コマ
ンド設定回路はＤＭＡ転送中に次回の［）ＭＡ転送コマ
ンドを設定可能なりＭＡコントローラ１と、ＤＭＡ転送
開始コマンドをＤＭＡ転送終了後にＤＭＡコン１−ロー
ラ１に設定するコマンド設定回路の機能をもつラッチ４
とを備えている。ラッチ４はＤＭＡ転送開始コマンドセ
ット信号５を保持し、コントローラ１よりのＤＭＡ転送
終了信号６によりＤＭＡ転送終了後にこのコマンドセッ
ト信号５をＤＭＡ転送開始コマンド信号３として出力す
る。As shown in FIG. 1, the DMA transfer start command setting circuit according to the present invention can set the next [)MA transfer command during DMA transfer, and the DMA transfer start command can be set by the MA controller 1 after the DMA transfer is completed. 1-Latch 4 that functions as a command setting circuit for setting roller 1
It is equipped with The latch 4 holds the DMA transfer start command set signal 5, and outputs this command set signal 5 as the DMA transfer start command signal 3 after the DMA transfer is completed according to the DMA transfer end signal 6 from the controller 1.

ＤＭＡコントローラ１はＤＭＡ転送の方法を決定するた
めのパラメータ設定信号２及びＤＭＡ転送開始を制御す
るＤＭＡ転送開始コマンド信号３により動作する。The DMA controller 1 operates based on a parameter setting signal 2 for determining a DMA transfer method and a DMA transfer start command signal 3 for controlling the start of DMA transfer.

したがって、ＤＭＡ転送中にラッチ４にて保持されたＤ
ＭＡ転送開始コマンドセット信号５はＤＭＡコントロー
ラ１のＤＭＡ転送終了信号６によりＤＭＡ転送終了後に
ＤＭＡ転送開始コマンド信号３としてセットされ、ＤＭ
Ａ転送終了後にパラメータ設定信号２及びＤＭＡ転送開
始コマンド信号３の入力によりＤＭＡコントローラ］は
動作し、ＤＭＡコントローラ１にＤＭＡ転送開始コマン
ドが設定される。Therefore, D held in latch 4 during DMA transfer
The MA transfer start command set signal 5 is set as the DMA transfer start command signal 3 after the DMA transfer is completed by the DMA transfer end signal 6 of the DMA controller 1, and
After the A transfer is completed, the DMA controller is operated by inputting the parameter setting signal 2 and the DMA transfer start command signal 3, and a DMA transfer start command is set in the DMA controller 1.

［発明の効果］ 以上説明したように本発明はＤＭＡ転送開始コマンドを
ＤＭＡ転送終了後ハードウェアにて直接ＤＭＡコントロ
ーラに設定可能にすることにより、ＤＭＡ転送中に、次
回のＤＭＡ転送のためのすべてのコマンドをＤＭＡコン
トローラに設定可能となり、高速な連続ＤＭＡ転送を行
なうことができる効果がある。[Effects of the Invention] As explained above, the present invention allows the DMA transfer start command to be directly set in the DMA controller by hardware after the DMA transfer is completed, so that all the necessary information for the next DMA transfer can be executed during the DMA transfer. commands can be set in the DMA controller, which has the effect of making it possible to perform high-speed continuous DMA transfer.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の構成を示すブロック図で必る。 FIG. 1 is a block diagram showing the configuration of the present invention.

Claims (1)

【特許請求の範囲】[Claims] （１）連続したＤＭＡ転送を行なうシステムにおいて、
転送中に次回に行なうＤＭＡ転送コマンドを設定可能な
ＤＭＡコントローラと、ＤＭＡ転送開始コマンドをＤＭ
Ａ転送終了後にＤＭＡコントローラに設定するコマンド
設定回路とを有するＤＭＡ転送開始コマンド設定回路。(1) In a system that performs continuous DMA transfer,
A DMA controller that can set the next DMA transfer command during transfer, and a DMA controller that can set the DMA transfer start command.
A DMA transfer start command setting circuit having a command setting circuit for setting a command to a DMA controller after the A transfer ends.
JP1890087A 1987-01-29 1987-01-29 Circuit for setting dma transfer start command Pending JPS63186357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1890087A JPS63186357A (en) 1987-01-29 1987-01-29 Circuit for setting dma transfer start command

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1890087A JPS63186357A (en) 1987-01-29 1987-01-29 Circuit for setting dma transfer start command

Publications (1)

Publication Number Publication Date
JPS63186357A true JPS63186357A (en) 1988-08-01

Family

ID=11984461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1890087A Pending JPS63186357A (en) 1987-01-29 1987-01-29 Circuit for setting dma transfer start command

Country Status (1)

Country Link
JP (1) JPS63186357A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011181029A (en) * 2010-03-04 2011-09-15 Ricoh Co Ltd Data transfer control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011181029A (en) * 2010-03-04 2011-09-15 Ricoh Co Ltd Data transfer control device

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