JPS6072451A - Block transfer system in unconfirming transfer - Google Patents

Block transfer system in unconfirming transfer

Info

Publication number
JPS6072451A
JPS6072451A JP58179222A JP17922283A JPS6072451A JP S6072451 A JPS6072451 A JP S6072451A JP 58179222 A JP58179222 A JP 58179222A JP 17922283 A JP17922283 A JP 17922283A JP S6072451 A JPS6072451 A JP S6072451A
Authority
JP
Japan
Prior art keywords
transfer
control device
input
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58179222A
Other languages
Japanese (ja)
Inventor
Koyo Oyama
尾山 幸洋
Fumio Adachi
安達 文夫
Hiroya Tanigawa
博哉 谷川
Kunio Fukuhara
福原 邦男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP58179222A priority Critical patent/JPS6072451A/en
Publication of JPS6072451A publication Critical patent/JPS6072451A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L13/00Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00

Abstract

PURPOSE:To realize the transfer of a control signal with minimum constitution by providing plural meanings to the control signal and deciding timewise agreement and sequential agreement to attain summarization and also introducing the concept as unconfirming transfer. CONSTITUTION:An input/output controller 1 transmits a transfer preparation request data 31 from a data signal output device 3 and a transfer preparation request signal 21 from a control signal output device 2. When the end of preparation is confirmed by a response data 41 and a response signal 51 from a device II, a transmission data 32 is given to a device 3 for transmission and a memory request signal 22 is outputted from the device 2. This operation is repeated by a fixed length's share at a prescribed period, the management of the number of times of reception of the confirming response signal 52 within a prescribed time from the device II is performed in parallel to confirm the normality of the number of times of transfer. Then the end signal 53 is transmitted from the device 2, and when the response signal 51 and the transfer result data 54 from the device II are received, the normality is confirmed and the transfer is completed. The data is transferred while neglecting a fault, in such a way, caused during the transfer.

Description

【発明の詳細な説明】 方式に関するものである。[Detailed description of the invention] It is related to the method.

従来のこの腫装置では,データの送受において制御信号
による確認動作を行なっており.Pft定の手順を踏む
ことからそのシーケンスに必要な最低時間間隔を短縮す
ることができ、ないという欠点が°:富2゜、7゜、*
zyt+ai74.4.。6.1゜信号でのブロック転
送方式を実現しようとするものである。□ 本発明はまた。転送速度を上げることのできるブロック
転送方式を実現しようとするものである。
This conventional tumor device performs confirmation operations using control signals when transmitting and receiving data. The minimum time interval required for the sequence can be shortened by following the Pft-determined procedure, but there is a disadvantage that there is no °: wealth 2 °, 7 °, *
zyt+ai74.4. . This is an attempt to realize a block transfer method using 6.1° signals. □ The present invention also includes: This is an attempt to realize a block transfer method that can increase transfer speed.

本発明は、制御信−弓に複数の意味を持たせ8時間的な
約束及びシーケンス的約束を決めることで本来の制御信
号の集約化を図9.また非確認転送という概念全導入し
てフレーム転送単位での確認を簡略化す為ことで制御信
号が少なく転送速度も上げることのできるブロック転送
方式を実現した□ ものである。
The present invention achieves the original aggregation of control signals by assigning multiple meanings to control signals and determining 8-hour commitments and sequence commitments. Furthermore, by introducing the concept of unconfirmed transfer and simplifying the confirmation of each frame transfer, a block transfer method that requires fewer control signals and can increase transfer speed has been realized.

本発明は、中央制御系からの制御によシ単独でブロック
転送制御を行なう入出力制御装置において、該入出力制
御装置ば制御信号ドライ・り/レシーバ、データバスド
ライバ/レシーバ、メモリ及び制御部等によ多構成され
1.対向入出力制御装置との間のブロック転送に際して
該入出力制御装置は、対向入出力制御装置に対して転送
準備要求データを送信データバス上に乗せ、転送準備要
求信号のオンによシ転送準備を起動して、その応答であ
る受信データバス上の応答データと応答信号のオンによ
シ、準備、完了を確認した後、該入出力制御装置からの
送信時には、送信データを送信データバス上に乗せメモ
リ要求信号をオンにする動作を一定周期で固定回数分線
シ返し行ない、−刃対向入出力制御装置は、データ受信
毎に確認応答信号を返送し、これを該入出力制御装置が
カウントして転送数の正常性を確認し終了動作へ移シ、
丑た該入出力制御装置受信時には、該入出力制御装置か
らの一定周期のメモリ要求信号によ勺゛対向人出力制御
装置が受信データバス上にデータを乗せ。
The present invention provides an input/output control device that independently performs block transfer control under control from a central control system, which includes a control signal driver/receiver, a data bus driver/receiver, a memory, and a control unit. It is composed of many things such as 1. When performing a block transfer with the opposing input/output control device, the input/output control device sends transfer preparation request data to the opposing input/output control device on the transmission data bus, and turns on the transfer preparation request signal to prepare for transfer. After confirming that the response data and response signal on the reception data bus are turned on, ready, and completed, when transmitting from the input/output control device, the transmission data is sent on the transmission data bus. Then, the operation of turning on the memory request signal is repeated a fixed number of times at a constant cycle, and the blade facing input/output control device returns an acknowledgment signal every time data is received, which is then sent back to the input/output control device. Count and check the normality of the number of transfers, then move to the end operation,
When receiving data from the input/output control device, the other person's output control device loads data onto the reception data bus in response to a memory request signal of a fixed period from the input/output control device.

確認応答信号を返送する動作を繰り返し、該人出力制御
装置は送信時同様に正常性を確認してi了動作へ移る。
The operation of returning the acknowledgment signal is repeated, and the human output control device confirms the normality in the same manner as when transmitting, and moves to the i-end operation.

 。.

以上のようなシーケンスに基づく固定長ブロック転送方
式において、該入出力制御装置主導型のクロック制御方
式であり、送受信のトリガ信号とその確認応答信号を独
立させることによシ該入出力制御装置主導のトリガ周期
でブロック転送できる。そして上記確認応答信号によシ
独立に転送語数の正常性のみを監視し、途中で異常が生
じてもブロック転送を中断しないという特徴をもつ非確
認ブロック転送方式を実現できる。
In the fixed-length block transfer method based on the sequence described above, this is a clock control method that is driven by the input/output control device, and by making the transmission/reception trigger signal and its acknowledgment signal independent, the clock control method is driven by the input/output control device. Block transfer can be performed with a trigger cycle of In addition, it is possible to realize an unconfirmed block transfer method which is characterized in that only the normality of the number of transferred words is independently monitored based on the above-mentioned confirmation response signal, and block transfer is not interrupted even if an abnormality occurs during the process.

以下に本発明の実施例を図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明方式を説明するための構成図でアシ、第
2図はそのシーケンス図である。ここでは入出力制御装
置1から対向入出力制御装置■への固定長ブロック転送
を行なう場合について説明する。
FIG. 1 is a block diagram for explaining the system of the present invention, and FIG. 2 is a sequence diagram thereof. Here, a case will be described in which fixed-length block transfer is performed from the input/output control device 1 to the opposing input/output control device (2).

人出力制御装置1′・では、制御装置6の指示によシデ
ータ信号出力装置3から転送準備要求データ31を送出
すると共に、制御信号出力装置2から転送準備要求信号
21を送出する。そして入出力制御装置■からの応答デ
ータ41と応答信号51を受けて準備完了を確認すると
、制御装置6は。
In the human output control device 1', the transfer preparation request data 31 is sent out from the data signal output device 3 according to the instruction from the control device 6, and the transfer preparation request signal 21 is sent out from the control signal output device 2. After receiving the response data 41 and response signal 51 from the input/output control device (2) and confirming that the preparation is complete, the control device 6 receives the response data 41 and the response signal 51 from the input/output control device (2).

メモリ1の送信データをデータ信号出力装置3へ2から
はメモリ号求信号22を出す。制御装置iM、 6は、
この動作を一定周期で固定長分だけ繰り哀し行ない、こ
れと並行して人出方制御装め■が4の一定時間内の確認
応答信号52の受信回数管扁を行ない1.転送数の正常
性を確認する。そしてす制御信号出力装置2よシ終了信
号53を送出しン入出力制御装置■からの応答信号51
と転送結電データ54を受信すると人出力制御装置■の
送1信の正常性と合わせて正常性の確認をしてブロン□
り転送を完了する。
The transmission data of the memory 1 is sent to the data signal output device 3, which outputs a memory request signal 22. The control device iM, 6 is
This operation is repeated for a fixed length at a fixed period, and in parallel, the crowd control system (1) counts the number of times the confirmation response signal 52 is received within a certain period of time (1). Check the normality of the number of transfers. Then, the control signal output device 2 sends out a termination signal 53 and a response signal 51 from the input/output control device ■.
When the transfer data 54 is received, the normality is confirmed together with the normality of the transmission from the human output control device ■, and the power is turned on.
complete the transfer.

このように本転送方式は、転送中に異:常が発′1生じ
てもこれを無視して続行する方式であり、転1・送数の
正常性が確認されなければ転送−了後、再□、転送が行
なわれるが2品質の良い□回想にお蛎では:異常発生は
ほとんど無いので本方式の有効性を発:揮できる。
In this way, this transfer method is a method that ignores any abnormality that occurs during transfer and continues, and if the normality of transfer 1 and number of transfers is not confirmed, after the transfer is completed, Re-□, transfer is performed, but with good quality □-recollection, there are almost no abnormalities, so the effectiveness of this method can be demonstrated.

ヶお。。ようヶいあり、114カヨ、。7・、、1硯デ
ータを入出力制御装置■へ転送する場合の他1.。
Gao. . There are 114 kayo. 7., In addition to the case of transferring 1 inkstone data to the input/output control device ■1. .

入出力制御装置1.で入出カ制御装口■のメモリ17の
データ転送を要求する場合がある。この場合も人出力制
御装置Iは、転送基イr11要求データと転送準備要求
信号とを送出し入出力制御装置■からの応答データと応
答信けを確認した後、メモリ要求信号を一定周期で固定
回数繰シ返し行なう。一方。
Input/output control device 1. In some cases, data transfer of the memory 17 of the input/output control device (2) is requested. In this case as well, the human output control device I sends out the transfer base Ir11 request data and the transfer preparation request signal, and after confirming the response data and response signal from the input/output control device ■, sends out the memory request signal at regular intervals. Repeat a fixed number of times. on the other hand.

入出力制御装置11では、メモリ要求信号受信毎にデー
タをデータバス」二にのせ確認応答信号を返送する。以
後の動作については、上述した送信時の場合と同様であ
る。
The input/output control device 11 puts data on the data bus 2 and returns an acknowledgment signal every time it receives a memory request signal. The subsequent operations are the same as in the case of transmission described above.

以上説明してきたように1本発明方式では転送準備を起
動し/ζ側の人出力制御装置のメモリ要求信号の送出周
期を独立させていることにより、転送速度を上げること
ができる。しかも転送中においては制御信号によ′る確
認動作を行なわないことから制御部を筒略化できる等の
効果がある。
As explained above, in the method of the present invention, the transfer speed can be increased by activating the transfer preparation and making the transmission period of the memory request signal of the human output control device on the /ζ side independent. Moreover, since no confirmation operation using control signals is performed during transfer, the control section can be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図υツ、本方式を適用する人出力制御装置のプロ、
り図を示し、第2図は本方式のシーケンス図を示す。 1.7・・・メモリ、2.11・・・制御信月出力装め
。 3.10・・データ信号出力装置、4,9 データ信号
入力装置、5,8・・・制御信号入力装置、θ112・
・・制御装置。 第1図 第2図
Figure 1.
Figure 2 shows a sequence diagram of this method. 1.7...Memory, 2.11...Control signal output equipment. 3.10...Data signal output device, 4,9 Data signal input device, 5,8...Control signal input device, θ112.
··Control device. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 1、 中央制御系からの制御により単独でブロック転送
制御を行なう入出力制御装置において、該入出力制御装
置と対向入出力制御装置との間で固定長ブロック転送を
行なう場合に、該入出力制御装置は対向入出力制御装置
に対して転送準備要求データと転送準備要求信号を送出
して転送準備を起動し、それに対する上記対向入出力制
御装置からの応答データと応答信号を確認した後、該入
出力制御装置送信時には、送信データを送信データバス
上に乗せ、メモリ要求信号オンにする動作を一定周期で
固定回数分繰シ返し行ない、一方、対向入出力制御装置
はデータ受信毎に確認応答信号を返送し、該人出ツノ制
御装置は一定時間内の上記確認応答信号を送信動作と独
立にカウントし転送数の正常性を確認して終了動作へ移
シ、また該入出力制御装置受信時には、メモリ要求信号
オンにする動作を一定周期で固定画数分繰り返し行ない
。 一方、対向入出力制御装置は上記メモリ要求イ1)号受
信毎に応答データを応答データバス上に乗ぜ確認応答信
号を返送する動作を行ない、該人出力制御装置が上記応
答データを受信すると共に、一定時間内の上記確認応答
信号をカウントし転送数の正常性を確認して終了動作へ
移り、終了動作中で正常/異常処理を行ない、プロ、り
転送中には制御信号の確認を行なわず途中で異常が発生
しても中断しないようにした非確認転送におけるブ「1
7り転送方式。
[Claims] 1. In an input/output control device that independently performs block transfer control under control from a central control system, when fixed-length block transfer is performed between the input/output control device and an opposing input/output control device. Then, the input/output control device sends transfer preparation request data and a transfer preparation request signal to the opposite input/output control device to start the transfer preparation, and receives response data and a response signal from the opposite input/output control device. After confirming, when transmitting data to the input/output controller, the transmission data is placed on the transmission data bus and the operation of turning on the memory request signal is repeated a fixed number of times at a constant cycle.Meanwhile, the opposing input/output controller An acknowledgment signal is sent back each time data is received, and the turnout control device counts the acknowledgment signals within a certain period of time independently of the transmission operation, confirms the normality of the number of transfers, and moves to the end operation. When receiving the input/output control device, the operation of turning on the memory request signal is repeated for a fixed number of strokes at a constant cycle. On the other hand, the opposing input/output control device performs an operation of multiplying the response data onto the response data bus and returning an acknowledgment signal every time it receives the memory request (1) above, and when the human output control device receives the response data, , counts the above acknowledgment signals within a certain period of time, confirms the normality of the number of transfers, moves to the termination operation, performs normal/abnormal processing during the termination operation, and checks the control signal during the transfer. The block “1” in unconfirmed transfer is designed to prevent interruption even if an error occurs during the transfer.
7ri transfer method.
JP58179222A 1983-09-29 1983-09-29 Block transfer system in unconfirming transfer Pending JPS6072451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58179222A JPS6072451A (en) 1983-09-29 1983-09-29 Block transfer system in unconfirming transfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58179222A JPS6072451A (en) 1983-09-29 1983-09-29 Block transfer system in unconfirming transfer

Publications (1)

Publication Number Publication Date
JPS6072451A true JPS6072451A (en) 1985-04-24

Family

ID=16062066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58179222A Pending JPS6072451A (en) 1983-09-29 1983-09-29 Block transfer system in unconfirming transfer

Country Status (1)

Country Link
JP (1) JPS6072451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128644A (en) * 1985-11-29 1987-06-10 Usac Electronics Ind Co Ltd Fully double transmission and reception test system
US7810229B2 (en) 2005-06-13 2010-10-12 Tomoegawa Paper Co., Ltd. Tape core wire wiring apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128644A (en) * 1985-11-29 1987-06-10 Usac Electronics Ind Co Ltd Fully double transmission and reception test system
JPH0453343B2 (en) * 1985-11-29 1992-08-26 Pfu Ltd
US7810229B2 (en) 2005-06-13 2010-10-12 Tomoegawa Paper Co., Ltd. Tape core wire wiring apparatus
US8336486B2 (en) 2005-06-13 2012-12-25 Tomoeagawa Paper Co., Ltd. Tape core wire manufacturing apparatus, tape core wire wiring apparatus and wiring method

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