JPS5970093A - Pal type clock phase detector - Google Patents

Abstract

PURPOSE:To obtain a PAL type clock phase detector outputting clocks reducing jitter with a simple constitution by combining a differential signal generator, an integrator, delay circuits, and an adder. CONSTITUTION:A digital video signal is applied to the differential signal generator 10. The generator 10 inputs the digital video signal and adds a signal Pe-2 passed through two delay circuits 6, 7 to a signal -Pe passed through an inversion gate 8 by the adder 9. The circuit 10 finds out the difference between the data pe-2 of two samples before and the data Pe at the present time and outputs Pe-2-Pe. Subsequently, the integrator 11 integrates chrominance subcarriers out of a digital video signal only for a burst period. The integration is controlled by an integration controlling signal indicating the same period. The integrated output can be used as a phase difference signal. The adder 13 adds the phase difference signal to a signal obtaining by delaying the phase difference signal by one horizontal scanning period to obtain a composite difference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a circuit for generating a signal synchronized with the chroma subcarrier of a received video signal in a PAL television receiver. With the recent progress in semiconductor and LSI technology, there is a tendency to replace conventional analog signal processing television receivers with digital signal processing. In that case, it is usually thought that the demodulated composite video signal is converted to a digital signal by an analogue digital converter (hereinafter referred to as ADC), and that the contrast and brightness control of the video and the demodulation of the color signal are performed by a digital circuit. This signal is processed by a digital-to-analog converter (hereinafter referred to as DAC) and then converted to an analog signal and displayed on a cathode ray tube.In such digital signal processing, it is easy to convert it into an LSI, and at the same time it is easy to use an IC. Almost no external parts are required, and adjustments in the manufacturing process can be eliminated or automated easily.However, ADCs and DACs require clocks, and the design of the circuit that generates them is important.

Purpose of the Invention The present invention has a relatively simple configuration and can obtain a clock with little jitter.Constitution of the present invention The present invention inputs a digital video signal, calculates the difference from the signal two samples before, and calculates the result. A difference signal generator to output, an output signal of this difference signal generator, and an integration control signal are input, and the output signal of the difference signal generator is integrated into a video signal during a burst period while being controlled by the integration control signal. an integrator that generates and outputs an error signal indicating a phase error between the burst and the sampling clock of the digital video signal; a delay device that inputs the error signal, delays it by one horizontal period, and outputs the signal; It is equipped with an adder that inputs the error signal from the integrator and the error signal from the delay device, adds the two to create a composite error signal, and outputs the result.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described. The following explanation will be limited to an example in which the system clock has a frequency four times that of the sending burst signal. The phase detector of the present invention is a part of a digitized clock recovery circuit as shown in FIG. used as.

The circuit shown in FIG. 1 is used to generate an ADC sampling clock when an analog video signal is digitized by ADCl.

FIG. 3 shows a block diagram of a phase detector in an embodiment of the present invention. In FIG. 3, a digital video signal is input, but this is the output of an ADC and is usually a digital signal with a total of 7 to 8 nodes. The difference signal generator inputs a digital video signal and generates a signal P8-2 which has passed through two delay circuits 6 and 7.
and the signal -P passed through the inverting gate 8. are added by adder 9. This circuit calculates the difference between the data P8-2 two samplings ago and the current data P8 and outputs Pe-2 - Pe.

This signal is always output during the input period of the input digital video signal. Difference signal generator 10 according to 6, 7, 8.9 above
is configured. Next, the integrator 11 integrates only the burst period of the chroma subcarrier in the digital video signal. This is controlled by an integration control signal indicating the same period. This is controlled by an integration control signal indicating the same period.

FIG. 2 shows details of sampling during the burst period. In FIG. 2, a indicates the magnitude of the synchronization signal, and b indicates half the burst amplitude. Since the input to the integrator 110 is Pe-2-Pe, N "4j-3-P4j-1 y P4j-2-
PJ I"4j-1-P4j+11 P+j-P4j+
2nd place is input continuously, but P4j-3 "4i-1
By selecting and integrating it times, we obtain Er'=Σ(P4H-s-P4j-1))-1. Here, k is assumed to be equal to the wave number of the burst.

Also, P4j −3 j P4j−2 ”4j−1 +
``4j is as follows.

P4,3= a+bsinθ P4,2=a+bsin (θ+-)=a
+bcos θP4,1= a+bsin (θ+yr
) = a-bsinθP4, = a+bsin
(θ+7) == a − b cos θ From the above equation, E,' becomes E'==2 kbsin θ as shown below, which can be used as a phase error signal.

This error signal is output from the integrator 11.

On the other hand, in PAL television broadcasting, the burst signal is shifted by 900 for each horizontal scanning line and sent, so the m-th error signal is Er'-Σ(P4j-3 ``4i-1))-1 = 2kbsinθ The (m+1)th error signal is = 2 kbgin (θ--), where the m and m + 1 suffixes indicate the mth and (m+1)th data and error signal, respectively.

The delay device in FIG. 3 delays Pn' by one horizontal scanning period, and the adder adds Pr' and Pr'. In this way, the composite error signal P is = 2kb sin
θ+2kb 5in(θ-1)=2 2 kb 5i
n(θ-1). Looking at this, the clock is drawn in between the two burst signals shifted by 9o0.

In the PAL system, demodulation of color difference signals is facilitated by sampling on the RY) and (BY) axes, which coincide with the -(B-Y) axis.

In the case of the NTSC system, a difference signal generator 10 and an integrator 11
A phase detector can be constructed in the same way, but in the case of the PAL system, it can be realized by adding a delay device 12 and an adder 13 to this. The delay device 12 is a latch circuit itself, and the adder 13 can also be composed of several tens of gates, so the difference signal generator 1
It has the advantage that it can be realized with a relatively small-scale addition compared to 0, the integrator 11, etc. Furthermore, as shown in FIG. 1, there is no need to change the blocks A-D converter 1, VCOX 5, 7, filter 4, and D-A converter 3 other than the phase detector 2 according to the present invention, so the PAL system and the NT
It can be said that there are few changes to the SC method.

Effects of the Invention As described above, by using the PAL phase detector according to the present invention, it becomes easy to construct a clock recovery circuit for both NTSC and PAL. Furthermore, the clock regeneration circuit shown here is suitable for IC implementation, and has the advantage of being usable as a digital television receiver.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a clock recovery circuit that can use the phase detector of the present invention, Fig. 2 is a waveform diagram for explaining details of sampling of the burst portion, and Fig. 3 is an embodiment of the present invention. FIG. 2 is a block diagram of a PAL clock phase detector in an example. 10... Difference signal generator, 6, 7... Delay circuit, 8... Inverting gate, 9... Adder, 11...
...Integrator, 12...Delay device, 13...Adder. Figure 1

Claims (1)

[Claims] A difference signal generator that inputs a digital video signal, calculates the difference with the signal two samples before, and outputs the result, and inputs the output signal of this difference signal generator and an integration control signal, and is controlled by the integration control signal. The output signal of the difference signal generator described above can be calculated by calculating the output signal contained in the video signal.
an integrator that creates and outputs an error signal indicating a phase error between the ramp clock and the ramping clock of the digital video signal; a delay device that inputs the error signal and outputs the delayed one horizontal period; and the integrator. A PAL method lottery 12 phase detection system equipped with an adder that inputs the error signal from the 12-bit error signal and the error signal from the delay device, adds the two, creates a composite error signal, and outputs it.