JPS59117870A - Digital vertical synchronizing device - Google Patents

Abstract

PURPOSE:To attain stabilization and rationalization of operation by processing a digital signal so as to obtain a vertical pulse in a television receiver. CONSTITUTION:A vertical synchronizing signal E is obtained from an inputted composite video signal and the signal E and an output G of a counter circuit synchronized with the signal E are applied to a control pulse generating circuit 7. The detected output is generated by adding both E, G and delayed at a delay means and when the added signal reaches a comparison level, the detected output is taken as a control pulse F to reset the counter circuit 6 and the pulse F is applied to a vertical pulse generating circuit 8. The vertical pulse generating circuit 8 generates a pulse of a prescribed pulse width based on the control pulse and the pulse is extracted as a vertical deflection pulse H. Thus, the vertical pulse is obtained by the digital signal processing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical synchronization device for a television receiver.

Conventional configurations and their problemsRecently, with the advancement of VLSI technology, conventional analog processing circuits are being digitized.Even in each circuit of a television receiver, input signals are processed by A/D converters. In the 0 digital signal processing method, which is being considered in many ways to obtain an output signal by quantizing it into a binary value and performing signal processing such as addition, subtraction, and squaring on the digital value, the resistors and capacitors used in the conventional analog method are Since almost no other parts are required, combined with the high integration of semiconductor integrated circuits, it becomes possible to significantly reduce the number of parts. Also, since there are no variations in parts, there is no need for adjustment, and there is no change over time.

Conventionally, vertical synchronization circuits used in televisions are analog circuits, and are generally configured as shown in FIG. The operation of FIG. 1 will be briefly explained below. The input signal in FIG. 1 is a composite video signal. From this composite video signal, horizontal and vertical synchronization signals A
is taken out. The extracted composite synchronization signal A is integrated by C and H in the vertical synchronization separation circuit 2, and only the wide vertical synchronization signal B is extracted and guided to the vertical oscillation circuit 3.

Vertical oscillation circuit 311'i is an oscillation circuit composed of R and C time constant circuits, and its oscillation frequency is the output of the vertical synchronization separation described above, that is, the frequency directly triggered by the vertical synchronization signal. The output C of the oscillation circuit is held in synchronization with the input synchronization signal.

OBJECTS OF THE INVENTION It is an object of the present invention to realize an analog vertical synchronization circuit like the conventional example described above by adding and multiplying digital signals quantized into binary values.

Structure of the Invention The present invention comprises an integrating circuit for integrating a composite synchronizing signal and extracting a vertical synchronizing signal, a counting circuit for counting a signal with a frequency twice the horizontal frequency, and a combination of the output of the integrating circuit and the counting circuit. A control pulse generation circuit that performs digit detection with the output and uses the detected output as a control signal to generate a control pulse so that the output of the counting circuit is synchronized with the vertical synchronization signal, and an output signal of this control pulse generation circuit. A vertical pulse generation circuit is provided to obtain a vertical pulse with a more constant pulse width, thereby obtaining a pulse that is digitally synchronized with a vertical synchronization signal. ○ Description of an Embodiment The following is an embodiment of the present invention. This will be explained with reference to FIGS. 2 and 3, which show the following.

First, the operation and configuration of each part in FIG. 2 will be explained.

The input composite video signal is subjected to synchronization separation by a synchronization separation circuit 4 to obtain a composite synchronization signal. This synchronous separation circuit 1 may be a conventional analog type circuit. If the input composite video signal is a digital signal quantized into binary values (generally a 7-8 pinpoint video signal), the horizontal-vertical synchronization signal in this composite video signal is 6-6 bits. Therefore, in the synchronization separation circuit 1, the composite video signal (7 to
The upper 5 to 6 bits of the 8 pins) may be used as a synchronization signal, and these 6 to 6 pin digital signals (synchronization signals) may be handled as a 1-bit signal via a gate.

The composite synchronization signal output from the synchronization separation circuit 1 is integrated by the vertical synchronization separation circuit 5, which is a low-pass filter constituted by an adder/subtractor, a multiplier, and a delay means, to extract only the vertical synchronization signal E having a wide time width. 〇On the other hand, the circuit corresponding to the analog vertical oscillation circuit (3 in Figure 1) includes a counting circuit 6 (presettable counter) that counts a signal (clock) with a frequency twice the horizontal frequency and a control pulse. A generating circuit 7 and a vertical pulse generating circuit 8 are provided.

The frequency (period) of the output of this counting circuit 6 is reset. Here, fH is the horizontal frequency (15, 1, 7
5KHz). Figure 3 shows the output of the counting circuit 6 as D/
The waveform of the A-converted signal is shown. In FIG. 3, the comparison level is set so that self-reset is applied so that the lowest frequency of the counting circuit 6 is 35 Hz K. That is, the counting circuit 6 is such that it counts 2 fH-31.5 KHz 900 times and then performs a self-reset and then applies 1. fa in the figure.

fb is preset data of the counting circuit 6 and becomes fb. Similarly, to set the minimum pull-in frequency of this vertical synchronizer to 45Hz, fa = 200°).If the vertical synchronization signal E is added as shown in FIG. The frequency is a frequency synchronized with the vertical synchronization signal E.

Therefore, by adding the vertical synchronizing signal E and the output signal G of the counting circuit 6 to the control pulse generating circuit 7, adding them together using an adder and delaying them using a delay means, this added signal is shown in FIG. When the comparison level is reached, a detection output is generated, which is used as a control pulse F to reset the counting circuit 6 and also to be supplied to the vertical pulse generation circuit 8. The vertical pulse generating circuit 8 generates a pulse with a constant pulse width based on the control pulse F, and takes it out as a vertical deflection pulse H.

As described above, a vertical pulse synchronized with an input video signal can be obtained by a vertical synchronization device using digital signal processing.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, by performing digital signal processing, almost no resistor or capacitor is required, so extremely stable operation can be obtained - and significant rationalization can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a vertical synchronization circuit using conventional analog signal processing, Fig. 2 is a block diagram of a digital vertical synchronization device according to an embodiment of the present invention, and Fig. 3 is a D/A conversion of the output of the counting circuit. FIG. DESCRIPTION OF SYMBOLS 1... Synchronous separation circuit, 2... Vertical synchronous separation circuit, 3... Counting circuit, 4... Control pulse generation circuit, 5... ...Vertical pulse generation circuit.

Claims (1)

[Claims] an integrating circuit configured with an adder/subtractor, a double multiplier, and a delay means so as to integrate the composite synchronizing signal to obtain a vertical synchronizing signal; and a counting circuit that counts a signal having a frequency twice the horizontal period. An adder and a delay means that detect the phase difference between the output of the integrating circuit and the output of the counting circuit, and use the detected output as a control signal to generate a control pulse to synchronize the output of the counting circuit with the vertical synchronization signal. A digital vertical synchronizer comprising: a control pulse generation circuit having a plurality of configurations; and a vertical pulse generation circuit that generates a vertical deflection pulse having a constant pulse width based on an output signal of the control pulse generation circuit.