JPS5970024A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To reduce a delay time and power consumption by constituting a titled circuit with a small number of elements. CONSTITUTION:Gate circuits G1-G17 have I<2>L constitution. Out of these gates, the gates G1-G9 constitute a T type flipflop circuit generating outputs reverse to each other at A and A' in 1/2 frequency of an input signal. One output of the flipflop circuit has two inputs and supplied to the 1st R.S flipflop consisting of the gates G10-G13 generating outputs reverse to each other at B and B' in 1/2 frequency and the other output is supplied to the 2nd R.S flipflop consisting the gates G14-G17 and having the same constitution as the 1st flipflop. The output of the 1st R.S flipflop is supplied to the 2nd flipflop at the same phase and the output of the 2nd flipflop is supplied to the 1st flipflop at the reverse phase.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency dividing circuit, and particularly to a frequency dividing circuit having an IL configuration.

Frequency divider circuits are not only circuits that handle digital signals, but also
It is also used in circuits that handle analog signals. for example,
The FM multiplex demodulation circuit utilizes the 19K H2 high lot signal included in the input FM composite signal to obtain a 75KI-1g signal, divides this signal to create 38KHz and 19KHz signals, and converts these signals. Performs FM demodulation operation based on the signal.

In recent years, there has been a high demand for low voltage and low current consumption in signal processing circuits, and the same holds true for frequency divider circuits. Further, analog signal processing circuits are often configured with bipolar transistors. For this reason, the frequency dividing circuit in the FM multiplex demodulation circuit is constructed of an IL that is capable of low voltage and low current operation and can be manufactured using a bipolar process.

FIG. 1 shows a conventional I2L frequency divider circuit. In FIG. 1, G1 to G, 3 are I2L gates,
°C output varies depending on the number of output fanouts. CK is a clock pulse input terminal;

λ, B, H, C, and C are output terminals of each frequency division stage. Furthermore, as is clear from the line connection relationships shown in FIG.
, and G17 to G28 each constitute a T-type flip-flop circuit, and output A receives a signal obtained by dividing the input signal supplied to terminal CK by 1/2, and output B receives a signal obtained by dividing the input signal supplied to terminal CK by 1/2.
The signal frequency-divided by /2 is output to output C, and the phase is 90
° Different signals are taken out respectively, and outputs A, B, and C are outputs A, B, respectively.

A signal with the opposite phase of C is obtained. Therefore, if a 75KHz signal phase-synchronized to the 19KH two-person pilot signal is supplied as an input signal using PLL technology, the output A will have a 38KHz signal.
19KHz signal on output B, 19KHz signal on output C
19 KHz with a phase difference of 90° are obtained.

The 38KHz signal of outputs A and A is sent to the demodulation circuit, and the output B
The 19 KHz signals of C and C are used for comparison with the input pilot signal and for determining the presence or absence of the input pilot signal, respectively.

FIG. 2 is a signal waveform diagram of each output with respect to an input pulse signal, and the operation of FIG. 1 will be explained using FIG.

First, outputs A and A will be explained. toK C, when clock CK is low level (L), output A rises, A
is level (H), then at tI the gate (jl
output beam, gate G3. Since the outputs of G4 both become H, the outputs of Gs and Or maintain the io state. t
2, the output of Gt is H, and the output of gate G5 is H
, G, and the output of gate G3 become H, the output of gate 06 becomes L, the output of G becomes H, and the output A becomes H9λ becomes L. In ts, gate G
1 output beam, gate G3. Since the output of G4 is 1 dH, G6. The output of G7 maintains the state at t2. t4
Then, the output of gate Gt is H, the output of G is L, the output of G4 is H, the output of G is H9, and the output of G3 is L, so the output of gate G6 is H and the output of G7 is L. , the output A becomes high, and A becomes H. After that, the same thing is repeated.

Next, outputs B and H will be explained. At to, the output B goes up and B becomes H, then at t2 the output A becomes L, and the output of Goo is the output of Hs014 t'iL + Gsa
The output of G is H, the output of 011 is H*, the output of G 12 is L
Since the output BFi, )l changes respectively.

n becomes L. At t4, the output ^ becomes H, and the gate G1
The output beam of °, G, , the output of G, 3 is H* (j 1
Since the output of 1G14 becomes L, the state of tj is maintained. ts
When this happens, the output A becomes L, and the output of the gate oto becomes H,
The output of 0 mouth is )l, G1. The output beam of G1. Since the output of G1□ becomes H, the output B and LB become H. At ts, output A becomes H, and Kate G! The output of O is L, GK, , G, the output of 3 is HoonG14
Since the output becomes L, the state of ts is maintained.

From now on, repeat these steps.

Next, the output of output C9C will be explained. 10, when the output C rises and C becomes H, the output A becomes H at t2, and the output of the gate Gt7 becomes L, GK, , G,.

The output of )l, G, the output of 8.021 becomes L,
Output and maintain the state of "to". At t4, output A is L
(9) Since the output B is H, the output of G21 is Le.
The output of GIG is) (, the output of G18 is H+, the output of 019 is L, and the output C is HlC. At ts, the output A is H, goo) (the output of 417 is high.

The outputs of G, , G, o become H, the outputs of Gt, , U2t become L, and the outputs C and C maintain the state at t4. tI
When it becomes I, the output A becomes L and the output B becomes L, so the output of the gate G21 becomes H, G2 . The output is L, G, 8
The output of L t is H. The output of G19 becomes H, and the output C becomes H. Repeat these steps from now on.

In this way, a frequency divider circuit that obtains a predetermined output was realized by the configuration using the IL gate shown in FIG.

However, although this circuit uses a 12L gate, it has a large number of elements and consumes a large amount of current.
Since the number of elements is large, the delay time is also long.

Object of the present invention (d) is to provide a frequency divider circuit that obtains a predetermined output with a smaller number of elements.

According to the present invention, there is provided a TW flip-flop that generates at least two outputs that are in opposite phases to each other at a frequency of 1/2 with respect to an input signal; 20R-8 type 7 lips and 70 lips, one output of the T type flip-flop is connected to the first
triggers an R-8 type flip-flop at the other output, and triggers a 20th R-8 type flip-flop at the other output;
The two outputs of the first -8 type flip-flop are added in phase to the second -8 type flip-flop.
(The two outputs of the -8 type flip 70 tube are connected to the first R, -
To obtain a frequency dividing circuit characterized in that it is applied to the input of an 8-type flip-flop in reverse phase.

In the present invention, a frequency divider circuit that obtains a predetermined output by connecting them is constructed using a 8-type flip-flop with a simple configuration and a small number of elements. Therefore, power consumption is reduced compared to the conventional method. , a reduction in delay time is realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which G1 to G1
7 is a gate circuit with an I"L configuration. Gates G to G
9 constitutes a T-type IJ tube flop circuit that generates outputs in opposite phases to A and A at 1/2 the frequency of the input signal, and one output (for example, output A) has two inputs. Further, outputs with opposite phases to each other at 1/2 frequency are generated at B and B)Gt.

The first 1 (, -8 type flip-flop) consisting of G13 to G13.

Supplied to the circuit. The other output (output A) is supplied to a second flip-flop circuit consisting of gates G14 to G17 similar to the first F-8 flip-flop. Furthermore, the output of the first f(-8 type flip-flop circuit) is supplied in phase to the second flip-flop circuit, and the output of the second flip-flop circuit is supplied to the first flip-flop circuit in opposite phase.

Next, the operation of the circuit shown in FIG. 3 will be explained. Since the steps from the clock input terminal CK to the outputs of A and A are completely the same as in the conventional circuit, the explanation will be omitted, and the operation after the outputs of A and A will be explained.

At t2, the outputs H and C are high, and the outputs H and C are H. At t2, the output A is H, the output C is high, and d is H, so the output of the gate GIG is L l (the output of jll is H
The output B becomes H and the output B becomes L.

Also, since the input is L, the gate G, 4. The output of G, is
It becomes H, and the output C1C maintains the state of to.

At t4, the output A becomes L, so the gate G1. ,G.

The output of becomes H, and the outputs B and B maintain the state of t2.
There is. Also, since the output K is H and the output B and HlB are L,
The output of the gate G14 becomes H, the output of Gls becomes H, the output C becomes H, and the output C becomes L. At t6, output A becomes H,
Since the output C is HlC, the output of Gso is )L,
The output of G and 1 becomes L, and the output of B and n becomes H.

Also, since the output ^ is L, goo)G, 4. The outputs of G and S become H, and the output C1d maintains the state at t4. t
, the output A becomes L, so the output of Gto, G, , becomes H, and the outputs H and B maintain the state at t6. Also, since the output K is H, the output B is high, and n is H, the output of gate G14 is H, the output of GK is low, the output C is high, and C becomes H, the same state as when to. , repeat these steps from now on.

As described above, according to the present invention, the same output signal can be obtained with 17 elements compared to the conventional 230 elements, and since the number of elements is reduced, current consumption can also be reduced by 26%. In addition, considering the delay time from the output of A to the output of B or C, the delay time is 3 gates in the conventional example, but it is 2 gates in the present invention, and the delay time is It can be shortened to 2/3. Therefore, the present invention can be applied to a leg circumferential device for FM multiplex, and its effects are very large.

It should be noted that the present invention is not limited to frequency dividing circuits having an IL configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a frequency divider for an FM multiplex using a conventional IL. FIG. 2 is a timing chart for explaining the operation of FIG. 1. FIG. 3 is a circuit diagram showing an embodiment of the present invention. FIG. 4 shows a timing chart for explaining the operation of FIG. 3. 01~G, 3...I2L gate, CK...
...Input terminal, IL HA, Jj, B, C
, C... Output terminal.

Claims (1)

[Claims] a first 7-lip flop that produces at least two outputs that are out of phase with each other at 172 frequencies of the input signal; and second and third 7-lip flops that each have two inputs and each produce two outputs that are out of phase with each other. adding one output of the first 70-lip flop to the second 70-lip flop and adding the other output to the third 70-lip flop, The output of the third 7-lip-flop is applied in phase to the input of the third 7-lip-flop, and the output of the third 7-lip-flop is applied to the input of the second 7-lip-flop.
A frequency dividing circuit characterized in that it applies signals in reverse phase to the inputs of a 7-lip flop.