JPS5969949A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable fine processing and multilayer wiring for improving the degree of integration of an element by forming a polycrystalline silicon layer on a substrate directly or through an intermediate layer, coating the predetermined region of the silicon layer with a mask and changing the polycrystalline silicon layer except the predetermined region into an oxide layer through selective oxidation. CONSTITUTION:A SiO2 layer 12 is formed through selective oxidation while using a nitride film 11 as a mask. A section except regions, which must function as a gate, a source and a drain, is coated with a resist film 4, and the oxide film can be etched, but window sections 6 are bored to the regions, which must function as the source and the drain, by using an etching liquid resisting the process such as a fluoric acid group etching liquid in the polycrystalline silicon. A polycrystalline silicon layer 13 of low resistance containing a V family element impurity such as phosphorus and a nitride film 11 are formed to the whole main surface of the substrate 1, the nitride films 11 are left only to electrode contact sections for the source, the gate and the drain, the oxide layer 14 is formed through selective oxidation while an impurity is diffused to the source and drain regions and the polycrystalline silicon layer, and an N type layer 7 is formed. When the nitride films 11 are removed, an MOSFET can be completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a miniaturized structure such as a diffusion region, an insulating layer, or an electrode layer.

For example, semiconductor devices such as MO8IC, which require a high degree of integration, generally require miniaturization.

It is desired to improve the processing accuracy of gate electrodes, etc., accurately control the shallow diffusion depth, and flatten the surface to facilitate multilayer wiring. 1st
Figures (5) to (c) show a method for manufacturing an N-channel MO8FET, in which an Si02 oxide film 2 is formed on the main surface of a P-type silicon substrate 1 [Figure 1 (5)], and then a CVD method is applied on top of the Si02 oxide film 2. A polycrystalline silicon layer 3 is deposited, and then photoetching is used to leave a resist film 4 in the area that will become the gate.
(Figure 1)). Using this resist film 4 as a mask, the polycrystalline silicon layer 3 and oxide film 2 other than the gate portion are removed by etching [FIG. 1(Q)]. Thereafter, the entire main surface is covered with an Si 02 film 5 by CVD method [FIG. figure("? )
, 'p4:f=Using the crystalline silicon layer 3 and the oxide film 2 as masks, impurities are introduced through this window by ion implantation or the like to form the N-type layer 7 [FIG. 1 η]. Next, after forming a passivation film 8 of SiN or SiO3 by, for example, the CVD method [FIG. 1(G)], this film 8 is
Open a contact hole for electrodeposition.

Gate electrode 9. by M vapor deposition film or the like. By providing the source and drain electrodes 10 [Fig.
A MO3F'ET having a structure including an electrode 9 is completed. In this λ method, the channel length is determined by the 8-sided microfabrication of the polycrystalline silicon layer 3, so as miniaturization progresses, the amount of side etching and its dispersion during etching of polycrystalline silicon can be kept within an allowable range. It is becoming increasingly important to keep this in mind. Recently, methods such as reactive ion etching have been developed as a method for etching polysilicon with minimal side etch, but there are restrictions on the underlying material and problems with contamination, making it difficult to apply to processing the polysilicon layer in the gate area. be. One more.

When multilayer wiring technology is required from the viewpoint of miniaturization and element integration, there is a problem in that wiring is prone to defects due to the difference in level between the eyebrows formed on the surface of the substrate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that allows fine processing and multilayer wiring in order to solve these problems and increase the degree of integration of elements.

The purpose of this is to provide a polycrystalline silicon layer directly or via an intermediate layer on a semiconductor substrate, then selectively oxidize the polycrystalline silicon layer in a predetermined region using a mask to oxidize the polycrystalline silicon layer other than the predetermined region. achieved by.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 (4-σ) shows the manufacturing process of a MOS FET according to the present invention, and parts common to those in FIG. 1 are denoted by the same reference numerals. An S + 02 film 2 is formed on a P-type silicon substrate l [FIG. 2(A)], and a polycrystalline silicon layer 3 and a silicon nitride film 11 are deposited thereon by CVD or the like [FIG. 2(A)]. (No.) Next, a photoetching method is used to leave the nitride film 11 only in the region that will become the gate [Fig. 2 (q)], and selective oxidation is performed using this nitride film as a mask to generate the 8102 layer 12 [Fig. 2 (q)]. Next, the regions that are to become the gate, source, and drain are covered with a resist film 4 (see Figure 2).The oxide film can be etched, but polycrystalline silicon can withstand this with an etching solution 1 such as hydrofluoric acid. A window 6 is opened in the region to become the source and drain using a suitable etching solution [FIG. 2 (F')]. According to this method, by appropriately selecting the oxidation conditions for polycrystalline silicon, it is possible to minimize the amount of side etching, and at the same time,
Since machining accuracy is not affected by etching liquid conditions, the machining accuracy of polycrystalline silicon is significantly improved. Next, as shown in Figure 2 O), phosphorus-like V
After forming a low-resistance polycrystalline silicon layer 13 containing multi-element impurities and a nitride film 11, 1 selective oxidation is performed, leaving the nitride film 11 only at the electrode contact areas for the source, gate, and drain (see Figure 2). At the same time, impurities are diffused into the source and drain regions and the polycrystalline silicon layer to form the N-type layer 7 [Figure 2 (■)].
. Thereafter, by removing the nitride film 11, a MO8FET having the structure shown in FIG. 2(J) is completed. The impurity-doped low-resistance polycrystalline silicon layer 13 serves as a diffused impurity source for forming the N-type layer 7 in a predetermined region, and also serves as a source and drain electrode and the gate along with the impurity-diffused polycrystalline silicon layer 3. The oxidized layer 14 (!) serves as an electrode, and the portion formed by selective oxidation serves as an insulating layer or a protective film.

As described above, according to the present invention, by partially oxidizing a polycrystalline silicon layer, microfabrication of the polycrystalline silicon layer can be performed by etching only the oxidized portion, and interlayer insulation of the oxidized portion can be performed. It is a good idea to use the part of the film that is not oxidized as a source of diffused impurities, electrodes, or wiring.

Not only is it effective for miniaturizing semiconductor devices and simplifying the manufacturing process, but the step part is only generated during the microfabrication process of polycrystalline silicon, and the rest of the area has a flat η plane, making it extremely suitable for multilayer wiring. It's advantageous.

[Brief explanation of drawings]

Figures 1 (A) to (F) are cross-sectional views showing the conventional manufacturing process of an N-channel MO8FET, and Figures 2 (A) to (J) show an example of the manufacturing process of an N-channel MO8FET according to the present invention. FIG. 1... Silicon substrate, 3-Polycrystalline silicon layer, 11
...Nitride film, 12.14...Rriding layer, 13...
Doped polycrystalline silicon layer. -fi 圀- -)PZ I'￥1

Claims (1)

[Claims] 1) After providing a polycrystalline silicon layer directly or via an intermediate layer on a semiconductor substrate, a predetermined region of the layer is covered with a mask, and selective oxidation is performed to remove polycrystalline silicon from areas other than the predetermined region. A method for manufacturing a semiconductor device, characterized in that the layer is an oxide layer. 2. In the method according to claim 1. A method for manufacturing a semiconductor device, characterized in that a generated oxide layer is removed by etching. 3) In the method according to claim 1. A method of manufacturing a semiconductor device, characterized in that a polycrystalline silicon layer to which impurities are added is used. 4) In the method according to claim 3,