JPS59684A - Electronic timepiece circuit - Google Patents

Abstract

PURPOSE:To prevent an error from occurring when a load with large power consumption is driven without increasing size, by disconnecting a power source and a feeding capacitor in response to a load operation signal and powering on the load with large power consumption through a delay circuit. CONSTITUTION:When the load operation signal is generated by an alarm switch 7 at alarm time, a transistor (TR)16 turns off and a light-load timer circuit body A is powered on by the capacitor 17 disconnected from the power source. At the same time, a gate 9 is opened through the delay circuit B responding to the load operation signal to control a TR10 according to a frequency division output f1; and a speaker 11 with large power consumption is fed from the power source and even when the power voltage drops owing to the large power consumption, the main body A operates normally. Thus, the electronic timepiece circuit which causes no error even when the load with large power consumption is driven is obtained without increasing its size.

Description

[Detailed description of the invention] This invention relates to an electronic timepiece circuit.

A conventional electronic clock is shown in FIG.

The oscillation frequency of the crystal oscillator 1 is divided by the dividing flip-flop group 2, and the divided output is waveform-shaped by the motor waveform shaping circuit 3, and then applied to the step motor 6 via the 7A 4.5. The step motor 6 is driven by the step motor 6, and the hour hand (not shown) is rotated by the step motor 6. Also, when the alarm setting time comes, turn on the alarm switch 7 and turn on the gate 8.
is opened, and a pulse signal flt, which is an intermediate output of the flip-flop group 2 for one branch, is applied to an alarm buffer 9 through a gate 8, and a speaker 11 is made to sound through a transistor 10. VDD is a power supply voltage applied to each circuit, 12 and 13 are resistors, and 14 and 15 are capacitors. However, in such a conventional electronic timepiece circuit, if the current flowing through the speaker 11 is large, the power supply voltage vDD may be extremely reduced to below the minimum operating voltage of the circuit, leading to a risk of malfunction.

In order to solve this problem, the power source for the transistor 10 that drives the speaker 11 may be made separate from the power sources for other circuits, but this increases the cost and increases the size.

Note that the above problem also occurred when lighting the lamp.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an electronic timepiece circuit that can prevent malfunctions due to a drop in power supply voltage when driving a load with large power consumption without increasing the size.

Part 51 of this invention! The entire example is shown in FIGS. 2 and 3.

That is, this electronic clock circuit, as shown in Fig. 2,
A power supply (vDD), a capacitor 17 charged by this power supply (vDD), a low power consumption hour hand circuit body A that operates by being powered by both ends of this capacitor 17, and a load caused by turning on the alarm switch 70. a transistor 16 that disconnects the power supply (VDD) from the capacitor 17 in response to an actuation signal; and a low power consumption delay circuit B that is supplied across both ends of the capacitor 17 and delays the load actuation signal for a certain period of time. , is equipped with a speaker 11 and - which consumes a large amount of power and is powered by the power supply (VDD) and operates in response to the output of this delay circuit B. To explain in detail, the alarm switch 7 is turned off before the alarm setting time is reached. is off, transistor ] 6 is on, and a clock with low power consumption, such as frequency dividing flip-flop group 2, etc. (b) A capacitor 17 is installed in the main body A.
The power supply voltage VDD is applied from both terminals of 0 to put it into the operating state, and the oscillation frequency of the crystal oscillator 1 is divided by υ by the division flip 70 knob group 2, and the motor waveform shaping circuit 3 converts the divided output into a waveform. After shaping, it is applied to the step motor 6 through the buffer 4.5 to drive the step motor 6, and the step motor 6 rotates the clock hands, and at this time, the capacitor 17 is also charged. .

In addition, when the alarm setting time comes, the alarm switch 7 is turned on and the transistor 16 is turned off, so that the clock circuit main body A with low power consumption such as the branch flip-flop group 2 etc.
The operation of t is sustained by the charging voltage of the capacitor 17, and t
In addition, when the alarm switch 7 is turned on, a load activation signal (high level voltage) as shown in FIG. Flip 7 for branch office on input terminal C
Adding a pulse signal f with a period T2 as shown in Figure #I3, which is the intermediate output of the 0-tube group 2, produces a signal as shown in Figure 3 (C) at the output terminal Q of this D flip-flop 18. The pulse signal f2' (r) with the period T2 is applied to the data input terminal D2 of the D flip-flop 19 constituting the delay circuit B, and the pulse signal f2' (r) with the period T2 is applied to the clock input terminal C2. A signal delayed by 1 to 21 hours is obtained, the gate 8 is opened with this delayed signal, and the pulse signal flt, which is the intermediate output of the branch flip-flop group 2, is passed through the gate 8 and added to the alarm buffer 9. 1
The speaker 11 is made to sound via 0'fr.

Clock input terminal C□ of D flip-flop 18.19,
The period T2 of the pulse signal f2 applied to C2 is set to be sufficiently larger than the cutoff time of the transistor 16, so that when the gate 8 opens and the speaker 11 starts to sound and a voltage drop occurs, the transistor 16 is always cut off.
Reference numeral 020 is the base resistor of the transistor 16, which switches the power supply to the clock circuit main body A, such as the branch flip-flop group 2, from the capacitor 17.

In this way, in this embodiment, just before the speaker 11 starts sounding, the power source and the clock circuit main body A, such as the frequency dividing flip 7° knob group 2, are disconnected, and the power is supplied from the capacitor 17 that has been charged in advance. Since the power is supplied to the clock circuit main body A such as the frequency dividing flip-flop group 2, the speaker 11
Even if the power supply voltage vDD decreases due to the ringing, there will be no malfunction.

Moreover, the power supply itself only makes the speaker 11 sound, and the drop in the power supply voltage vDD is also small.

# Other embodiments of this invention! This is shown in Figures 4 to 6.

That is, this electronic clock circuit uses a low power consumption timer circuit C supplied from both ends of the capacitor 17 to turn on the transistor 16 again a certain period of time after the load operation signal is generated (after the alarm switch 70 is turned on). By connecting the power supply to the capacitor 17, the voltage across the capacitor 17 becomes ■.

is designed so that the voltage does not drop below the minimum operating voltage VDD (min) to the clock circuit main body, and in this way the speaker 11
The power supply voltage ■DD can be reapplied to the capacitor 17 during the ringing of the power supply voltage ■ゎ. This is because D is extremely reduced only when an inrush current flows when the speaker 11 starts sounding, and thereafter becomes a stable special voltage vDD(1) higher than the minimum operating voltage V (min).

To explain in more detail, when the alarm setting time is reached,
At t+tI'i, the alarm switch 7 is off, and as shown in FIG. 5, there is no load activation signal (low level), the gate 20 is closed, the transistor 16 is turned on, and the capacitor 17 is charged.

The voltage V across this capacitor 17. (=vDD) is applied to the clock circuit main body A, and it becomes in an operating state similar to the one in FIG.

When the alarm setting time t arrives, press the alarm switch 7.
is turned on to generate the load activation signal (high level) shown in Figure 5, and this load activation signal opens the gates 20 and 21, and the pulse signal f, which is the intermediate output of the frequency dividing flip 7o horn group 2, is applied. From time t0 onward, the data is added to the counter 23 via the game (game) 21 as shown in ) of FIG. This counter 2
3, as shown in FIG. 5 (to), the output is inverted from low level to high level at the first pulse of Ilk, and after a predetermined number of pulses have been counted, the output returns to low level again.

The high level output of the counter 23 is 21? i- through transistor]6 and turns off transistor 16. When the transistor 16 is turned off, the clock circuit main body A is supplied with power from the capacitor 17.
Maintain operational status.

On the other hand, the load operation signal caused by turning on the alarm switch 7 is applied to the gate 8 through the entire delay circuit B, and the speaker 11 sounds with a delay of T2 to 2T2 hours after the load operation signal is generated, similar to the one in FIG.

After time t0, the timepiece circuit main body A is supplied with power from the capacitor 17 as described above and continues to operate.

As a result, the voltage across the capacitor 17 is V. The voltage V across the capacitor 17 gradually decreases. Before the voltage reaches the minimum operating voltage V (min) (at time 12 after time t has passed from time t to time D), the output of timer circuit C becomes a low level, and transistor 16ft is turned on again to supply power to capacitor 17. Connect the 1 time [2 onwards, a stable special voltage vDD (1) to the clock circuit body A? Add r.

In this embodiment, the timer circuit C turns on the transistor 16 and the capacitor 1 only for a certain period of time after the alarm switch 70 is turned on.
7 and the power source are separated, the voltage at both ends due to discharge of the capacitor 17 is ■. It is also possible to prevent malfunction of the clock circuit main body A due to a decrease in the temperature.

As described above, the electronic timepiece circuit of the present invention includes a power supply, a capacitor charged by the power supply, a timepiece circuit main body that consumes little power and operates by being powered from both ends of the capacitor, and responds to a load activation signal. a switch element that disconnects the power source from the capacitor; a low power consumption delay circuit that is powered from both ends of the capacitor and delays the load activation signal for a certain period of time; and an output of the delay circuit that is powered from the power source. Since the device is equipped with a load that consumes a large amount of power and operates in response to a load that consumes a large amount of power, it is possible to prevent malfunctions caused by a drop in the power supply voltage when driving a load that consumes a large amount of power without increasing the size of the device.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional electronic clock circuit, Fig. 2 is a block diagram of one embodiment of the present invention, Fig. 3 is a time chart thereof, and Fig. 4 is a block diagram of another embodiment of the present invention. The block diagram of the example and FIG. 5 (4) to (2) are its time charts.

Claims (1)

[Claims] (1) A power source, a capacitor charged by the power source, a single-needle circuit main body with low power consumption that is operated by being powered from both ends of the capacitor, and the power source and the capacitor are connected in response to a load activation signal. a switch element to be disconnected;
A delay circuit with low power consumption that is supplied with power from both ends of the capacitor and delays the load activation signal for a certain period of time, and a load with high power consumption that is supplied with power from the power source and is activated in response to the output of the delay circuit. Electronic clock circuit port (2)
2. The electronic timepiece circuit according to claim 1, wherein the switch element reconnects the distributed power source to the capacitor after a predetermined period of time has elapsed after the load activation signal is generated.