JPS596845U - Mounting base for hybrid integrated circuits, etc. - Google Patents
Mounting base for hybrid integrated circuits, etc.Info
- Publication number
- JPS596845U JPS596845U JP10190782U JP10190782U JPS596845U JP S596845 U JPS596845 U JP S596845U JP 10190782 U JP10190782 U JP 10190782U JP 10190782 U JP10190782 U JP 10190782U JP S596845 U JPS596845 U JP S596845U
- Authority
- JP
- Japan
- Prior art keywords
- mounting base
- integrated circuits
- hybrid integrated
- recesses
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案混成集積回路等の取付基体の一実施例を
示す平面図、第２図は第１図のＩ−Ｉ線 上の断面
図、第３図は第１図の説明に供する線図、第４図は本考
案の他の実施例の要部を示す断面図である。
１は絶縁基体、２ａ及び２ｂは夫々凹部、３ａ。
３ｂ及び３Ｃは夫々ピン、４ａ及び４ｂは夫々混成集積
回路、６は金属板端子である。Fig. 1 is a plan view showing an embodiment of the mounting base for the hybrid integrated circuit of the present invention, Fig. 2 is a sectional view taken along the line I-I of Fig. 1, and Fig. 3 is provided for explanation of Fig. 1. The diagram and FIG. 4 are cross-sectional views showing essential parts of another embodiment of the present invention. 1 is an insulating base, 2a and 2b are recesses, and 3a. 3b and 3C are pins, 4a and 4b are hybrid integrated circuits, and 6 is a metal plate terminal.
Claims (1)
部に導電性のピンを設け、該ピンの一端部及び他端部が
上記相隣れる凹部に夫々露出する様にしたことを特徴と
する混成集積回路等の取付基体。A plurality of recesses are provided in the insulating substrate, and conductive pins are provided on the walls adjacent to the adjacent recesses, and one end and the other end of the pins are exposed to the adjacent recesses, respectively. Features a mounting base for hybrid integrated circuits, etc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10190782U JPS596845U (en) | 1982-07-06 | 1982-07-06 | Mounting base for hybrid integrated circuits, etc. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10190782U JPS596845U (en) | 1982-07-06 | 1982-07-06 | Mounting base for hybrid integrated circuits, etc. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS596845U true JPS596845U (en) | 1984-01-17 |
| JPH0215324Y2 JPH0215324Y2 (en) | 1990-04-25 |
Family
ID=30240440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10190782U Granted JPS596845U (en) | 1982-07-06 | 1982-07-06 | Mounting base for hybrid integrated circuits, etc. |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596845U (en) |
-
1982
- 1982-07-06 JP JP10190782U patent/JPS596845U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0215324Y2 (en) | 1990-04-25 |
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