JPS5966716A - Sequence program debugging device - Google Patents

Abstract

PURPOSE:To confirm the executing state without stopping a program by providing an execution address storage memory in which an executed address is written and read and comparing the executed address with an address set optionally. CONSTITUTION:A sequence controller is constituted with a program storage memory 3 storing a data required for the program execution and a main controller 2 having an operating device and a sequence program is monitored. An objective address is set by a setter 1 and inputted to the main controller 2, and the program address during execution at a comparator 4 and the said objective address are compared. Further, an execution address data is written sequentially to an address storage memory 6 and the write is interrupted by the comparison output of the comparator 4. The address data stored in the memory 6 is read at a memory readout device 7 to know the process to reach the objective address and displayed on a display device 8 by tracing back to the objective address.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a sequence program debugging device that enables online monitoring of program execution operations in a sequence controller VC.

Technical Background of the Invention and its Problems Conventionally, sequence controllers have been mainly of the type that repeatedly executes a continuous program. In the case of ``Tenoizh'', the online monitor for the target command or block was iiJ function.

However, in recent years, among the sequence controllers used for trigger control and general work, there are also sequence controllers that have branch instructions, repeat instructions, etc., rather than just replacing relay sequences. are doing.

In such a sequence controller equipped with branch instructions, in addition to the continuous program operations as before, there are also addresses that are not executed due to branch instructions, so it is difficult to determine which address is currently being executed. It is difficult to check whether the program is running at any address, and it is no longer possible to monitor the program operating status at any address as before. Therefore, a lot of time is required, especially when debugging a program or analyzing a program when a problem occurs.

For example, when debugging a program, it is a two-time method to add instructions or blocks for each branch destination to know that the branch has been taken, delete those instructions after debugging, and then check the final operation. I was taking it.

In addition, when analyzing problems, desk studies are more important than checking on actual machines, and investigations using actual machines are already taking up a lot of time.

Purpose of the Invention The purpose of the present invention is to achieve the following by using branch instructions etc.
In sequence controllers, where it has become difficult to know the program operating status, it is important to monitor the route to a desired program line address without stopping the program.
The f/program debug device is located at the tl-obtainer.

A miscellaneous aspect of the invention The present invention repeatedly executes a program, and includes an execution address storage memory for storing the address of the executed program, a device for arbitrarily setting the program address, and an address set by the address setting device. , executed iL
a comparator for comparing the address of the program in the program;
A percentage loading device that successively stores the addresses being executed into the execution address storage memory, a reading device that reads the contents of the execution address storage memory, and a display device that displays the output of this successive reading device are connected to the sequence controller. 7 and stop the program from the specified address.
) · It is characterized by making it possible to know the program center line status.

Embodiment of the Invention FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. 1
is an address setting device, 2 is a royal control device, 3 is a program storage memory, 4 is a comparison device, 5 is a memory writing device, 6
1 is an address storage memory, 7 is a memory reading device, and 8 is a display device. 1, 4, 5, 6°7.8 are added to the conventional sequence controller when implementing the present invention. Each signal a % k is used for the following control, respectively.

The signal a is transmitted from the address setting device 1 to the main 161j control 2.
This is address setting request No. 11 to be output to.

The signal S is an address data signal set in the address setting table il, and is output to the main controller 11, the comparison device 4, and the memory reading device 7. Signal C is used as a signal to distinguish whether the address data signal outputted from the address setting device 1 is to be used for the comparator, t4, or the memory reading device 7, and is output to the main control device f2. . The signal d is a signal for writing a comparison address into the comparison device 4 as a result of the determination of the signal C by the main control @1i12.

The signal e is a continuous signal used by the main controller 2 to retrieve data necessary for program execution from the program storage memory 3, and is also output to the comparator 4, memory 1, and viewing device 5 at the same time.

The signal f is a program execution address data signal outputted from the main control device 2 to the program storage memory, and is outputted to the comparison device 4 and the memory writing device 5 at the same time. The signal g is a write request signal outputted from the memory IJ it loading device +t 5 to the address storage memory 6. The comparison device 4 compares the signal S and f, and the result is sent to the memory reading device #5, the main controller 2, and the display device 8.
This is the signal to be output to. Signal 1 is a signal used by main controller C 2 to input a read address to memory read device 7 . The signal J is a continuous output signal used by the memory continuous output device 7 to retrieve the contents of the address storage memory 6. The signal is an address data signal output from the address storage memory 6, and is output to the display device 8 via the reading device t7 and the main control device t2.

The main control device 2 is assumed to have a central control device, an arithmetic unit, an input control device, an output control device, and a working memory, which are the basic functions of a processor.

If you now want to know that a desired program execution address has been executed and check the progress up to that address, this is accomplished by the following operations in this configuration.

First, signals a, b, and c are outputted to the main controller 2 by the address setting device 1 in order to notify the comparator 4 of the target address. The main control device 2 receives a signal a from an input control device, an output control device, an arithmetic control device, and a central control device, which are provided as basic functions.

The contents of b and c are output to the comparator 4 as a signal d and a signal s from the device 1. The comparator 4 learns the comparison target address from the signals s and d from the device 2 and then uses the signals e and d.
The program address being executed from f is monitored and compared with the target address.

When executing a program, the main control unit fIL2 generally reads the program contents from the program execution address to the program storage device 3. By simultaneously outputting e and f to the comparison device 4, it becomes possible to monitor the program address being executed in the comparison device 4.

Memory writing device f5, like device 4, has signals 1je,
From f, the address of the program currently being executed is known, and while checking the signal indicating that the target address has been detected in the device 4, the execution address data is executed in the address storage memory 6 using the signal f2g. Kua included,
Comparison μ: 1. Address data writing to the memory 6 is interrupted when the target address is detected by the signal hVC from the path 4. The signal 11 output from the comparison device 4 is
:2 to inform the display device 8 that the desired address has been executed.

Next, the equipment engineer outputs signals a and Jc to the equipment 2 in order to know the progress up to the desired address.

At this time, the address data already output as a signal is stored in the memory 6.
Add the memory address of . The main control device 2 outputs a signal i for reading the contents of the address storage memory 6 and an address data write code b to the memory reading device 7 from the signals a, b, and c.

The memory reading device 7 outputs signals i and b for reading out :d in the address storage memory 6 from the aforementioned signals i and b to the memory 6, and reads the contents of the address storage memory 6 from the signal k which is the content of the memory 6. Retrieve the stored address data,
It is output to the display device 8 via the main control device 2.

Hereinafter, in the address setting device 1, the address storage memory 6
By changing the address pointed to by the pointer, it is possible to output to the display device 8 the progress of the addresses until the desired program execution address is reached.

FIG. 2 is an application of the configuration sequence of FIG. 1 to implement the invention. 1 to 8 are the same devices as in FIG. Also,
Direct numbers a to k also indicate the same content. In FIG. 2, a sequence controller consisting of a main controller 2 and a program storage memory 3 is configured so that the components 1, 4, 5, 6, and 7.8 necessary for realizing the present invention can be separated. The connection points with 1, 4, 5, 6, 7.8 are signals e,
Only f. Therefore, it is technically easy to make a device consisting of 1.4.5, 6, 7, and 8 detachable from a sequence controller, so it is possible to add a page UI to the sequence controller's hardware or software. (f) The non-inventiveness becomes Meigen-cho ml without being lost.

Effects of the Invention As described above, according to the present invention, by using the branch h6 instruction, it is possible to determine the desired program execution address even in a sequence controller in which it is difficult to prevent a program from misbehaving. The time spent on debugging and analyzing problems can be greatly reduced by making it possible to check if the program can stop the malfunction.
It is possible to create high-quality programs because it reduces Jt and allows for more complete IJ program debugging.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 442 is a block diagram of another one-dog proportional system of the present invention. l... Address setting device 2... King I control device 3... Program storage; l, E-I+4... Comparison device 5... Memory writing device 6... Address storage memory 7...・Memory i leakage device 8...Display device (7317) Representative patent attorney Noriyoshi Norichika (6 (1 person) Figure 1)

Claims (1)

[Claims] An address setting device that repeatedly executes one round of the program and can arbitrarily set the executed storage memory and program address, and a comparison device that compares the address set by the address setting device and the address of the program being executed. , a writing device for writing the address being executed into the successive execution address storage memory, a reading device for reading out the contents of the execution address storage memory, and a display device for displaying the output of the above-mentioned successive writing device are connected to the sequence controller. A sequence program debugging device that makes it possible to trace back to a specified address and find out the program execution status without stopping the program.