JPS58142443A - Event recorder - Google Patents

Abstract

PURPOSE:To measure automatically how many times events to be checked are generated in a specified program by providing a microprogram which reads out the content of a counter, writes it in a designated address in a main storage device, and resets the content of the counter to zero. CONSTITUTION:A counter 29 and a data bus 30 are provided for a conventional device and the content of the counter 29 is given to a data processing circuit 1. The head address of a microprogram processing a machine language instruction is set to a micro address search register 12, the content of the counter 20 is reset to zero and a specified program is run. When the specified program is finished, the counter 29 is stored with the number of times of executions of the machine language instruction taking the micro address set to the register 12 as the head address of microprogram is stored in the counter 29. When the micro instruction reading out the content of the counter 29 is executed, the number of times of executions stored in the counter 29 is written in the specified address of a main storage device 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device having a microprogram control function.

A conventional device of this type is shown in FIG. In the figure, (1) is a data processing circuit, (2) is a control circuit,
(alti signal line, (4) is microinstruction register, (
5) is a signal line, (6) a control memory that stores the Fi microprogram, and (7) a microinstruction from the #i control memory.
■Sequence control circuit that outputs the address signal to be read next, (8) is the address signal, (9) H data bus,
Q□if microinstruction bus, 0η is clock generation circuit,
(6) is a micro address search register, (to) is a data bus, Q4Fi comparator, (to) is a data bus, (to) is an address search mode control circuit, αη, Q8. (to) are signal lines, (e) is the main memory, (c) is the data bus, (a) is the instruction register, is the data bus, (
c) is an instruction decoding circuit, (c), c! 4 is a data bus, @ is an operation panel, and @ is a signal line.

Next, the functions of each part will be explained. The data processing circuit (1) is controlled by a control signal input from the control circuit (2) via the signal line (3), processes 6 types of data, and reads the data from the main memory (e) via the data bus Q1. The executed machine language instructions are held in an instruction register (2) via a data processing circuit (1) and a data bus. Instruction decoding circuit (c)
decodes the machine language instruction in the instruction register and generates the start address of the microprogram for executing the instruction. This start address is set in the sequence control circuit (7) via the bus (2) and given to the control memory (6)K via the address bus (8). Microinstruction register (4
) holds microinstructions read from control storage (6). Part of this microinstruction is input to the control circuit (2) via the signal line (5), and the other part controls the sequence control circuit (7) via the microinstruction bus α0 to determine the next address signal. do.

A specific microinstruction address is set in the microaddress search register (6) via the data bus Q3.

The microinstruction address input via the comparator Q4tj address bus (8) is compared with the contents of the microaddress search register α input via the data bus AS11rh, and if the two match, a logic "1" is sent to the signal line 0η. Outputs the signal. Address search mode control circuit (16Fi
For example, it consists of a 1-bit memory and an AND gate, and the 1-bit memory is set or reset by a signal on the signal line (17), and when this memory is set, only the signal on the signal line (17) A signal is output to signal line 0→. When the signal on the signal line 0 is logic "1", the operation j of the clock generation circuit is stopped. The operator is at the control panel.
The information from the data processing circuit (1) is given to the data processing circuit (1) via the signal line (c), and the information from the data processing circuit (1) is sent to the signal lI.
It is displayed on the display device of the operation panel via M.

Next, the operation of the circuit shown in FIG. 1 will be explained. When executing a program stored in the main memory tiOVc,
The machine language instruction to be executed first from the main memory is set in the output instruction register, the instruction decoding circuit (c) generates the start address of the microprogram that processes this machine language instruction, and the sequence control circuit (7) This start address is held and the control memory (6) is accessed via the address bus (8)f, and the microinstruction at the above-mentioned start address is issued to the microinstruction register (4). The read microinstruction is sent to the control circuit (2) via the signal line (5).
) to operate the data processing circuit (1), and also to control the sequence control circuit (7) via the microinstruction bus to determine the next microinstruction address. When the execution of one microinstruction is completed, the microinstruction read out by the next microinstruction address specified by the sequence control circuit (7) is executed, and in this way, the microinstructions are executed one after another. A microprogram that processes machine language instructions held in the instruction register executes a microinstruction to find the machine language instruction to be executed next Km, and when the processing of one machine language instruction is completed, the next machine language instruction is executed. The flow of the microprogram is moved to the start address of the microprogram to be processed.

On the other hand, the flow of the microprogram may be stopped at a desired point in order to debug the microprogram and check the operation of the circuit. In such a case, set the first microinstruction address of the microprogram that processes the desired machine language instruction in the microaddress search register by operating the operation panel ■, and set the logic "1" in the address search mode control circuit Q*. ” signal is set.

When the desired machine language instruction is read into the instruction register (2) and an address signal identical to the contents of the micro address search register O2 is output on the address bus (8), a logic "1" is output on the comparator Q4Fi signal line αη. This signal passes through address search mode control (b) path αQ and becomes a signal on signal line Q to clock generation (b) path (11).
) stops working. The clock generation circuit anFi generates clock pulses that provide the timing for the operation of all the circuits in the device shown in Figure 1, so when the operation stops, the state of the circuit at that point is maintained and the signals on each signal line are It is possible to perform tasks such as observing. When it is no longer necessary to perform such observation work, it is sufficient to set the address search mode control circuit αeK logic "0" signal. If this is done, the signal on the signal line αη will be blocked by the address search mode control circuit OQ and will not be output to the signal line (I).

By the way, various efforts have been made to improve the ratio of performance to circuit size in this type of data processing device, but for this reason, K is not suitable for which machine language instruction processing or the circuit for specific processing. The question is, what should we focus on?

K, who is studying this problem, needs to investigate which machine language instruction or which process has been executed and how many times in various programs, and for this investigation, conventional equipment uses the signal ll1.
lQ'? ) A counter was installed outside the device to take out the above signal and count the number of times this signal became logic "1".

Therefore, the conventional method has the disadvantage that the signal on the signal line U is taken out of the device, a counter is provided outside the device, and some kind of manual labor is required to read the counter and store the read count value. there were.

This invention was made in order to eliminate the drawbacks of the conventional methods as described above, and is a data processing method that can fully automatically measure how many times an event to be investigated occurs in a predetermined program. f! I! The purpose is to provide equipment.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, symbols (1) to @ indicate the same or equivalent parts as those in FIG. . 4 is a counter, and C1) sends the contents of the counter (G) to the data processing circuit (11) via a data bus.In addition, the instruction code of the machine language instruction is given as a parameter to the control memory (6) shown in Figure 2. Table 1 shows the start address of the microprogram that processes the machine language instructions.

□・:) Set micro address search register Ql
A microprogram named 1.1 and a microprogram that reads the contents of the counter and writes them to a designated address in the main memory (7) and resets the contents of the counter to zero are stored.

KFi measures the number of executions of a specified machine language instruction in a predetermined program to be measured using the device shown in Figure 2. First, the instruction code of the machine language instruction is given as a parameter, and the machine language instruction is processed. The first address of the microprogram is set in the microaddress search register cLIK (this is done by executing the above-mentioned microinstruction in the control memory (6)). Next, the content of the counter is reset to zero, and then the predetermined program is run.

In the same way as explained with reference to FIG.
Since there are cases where a signal of "1" is output, this logic "1" is output.
” signal, add 1 to the contents of the counter. When the above-mentioned predetermined program is completed, the counter holds the number of executions of a machine language instruction whose starting address of the microprogram is the microaddress set in the microaddress search register (2). Next, when a microinstruction to read the contents of the counter is executed, the number of executions held in the counter is written to a predetermined location in the main memory.

The above process is performed for each machine language instruction that requires investigation.

In the example shown in Fig. 2, only one set of micro address search register (2), comparator αΦ, and counter is provided, but by providing multiple sets, the execution of each machine language instruction of multiple types is possible. You can check the number of times at the same time. Furthermore, by giving the instruction code of a machine language instruction as a parameter, the start address of the microprogram that processes the machine language instruction is set in the micro address search register (
6), a microinstruction address may be given directly, and the contents of the counter may be written to a register or the like that can be operated by machine language instructions instead of being written to the main memory &.

As described above, according to the present invention, by simply adding hardware and related programs, the specified machine language instruction statement tfi (and) the processing of the specified rod can be executed several times during the execution of a predetermined program. K11lI easily executed
can be determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of the present invention. (8)...Micro instruction address line, (6)...Micro address register, α4...Comparator, 4...
Counter. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Shin Kuzuno −

Claims (1)

[Claims] In an event recording device that records how many times a specified machine language instruction statement #i (and) a specified type of processing is executed by controlling a microprogram while a specified program is being executed, at least one A micro address search register, each comparator provided corresponding to each of the micro address search registers, each counter provided corresponding to each of these comparators, and a control storage for storing a micro program. , a sequence control circuit that sequentially outputs address signals in order to read out microinstructions from this control memory, and the above-specified machine language instruction statement 1d (and) the beginning of the microinstructions that are read out to execute the process of the specified number of shares. means for respectively setting a numerical value indicating an address in the at least one micro address search register to reset the count value of each of the counters; means for outputting a signal when the content matches the address signal of the output of the sequence control circuit and counting the number of times this signal is outputted by a corresponding counter, and each of the above counts when the predetermined program is completed and means for latching the output of the event recording device.