JPS62162105A - Flow chart type programmable controller - Google Patents

Abstract

PURPOSE:To improve program debugging function by making it possible to know not only the course of execution of a user program but also control input/output signal information of a point of time and internal control information. CONSTITUTION:A trace instruction is set at an arbitrary point in a user program. When the trace information is read out from a user program memory 5, control input/output signal information and internal control information designated by the operand section of the trace instruction are stored in a buffer B2. Processing is made until the buffer 2 is filled. Information stored in buffers B1 and B2 can be displayed in the CRT of a console 4 or printed out by switching to a tool service mode and giving command to read information by the console 4. Thus, the program debugging is made based on information outputted to outside.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement in a flowchart type programmable controller (hereinafter referred to as PC) that serially processes a user program t written in a flowchart type along its flow.

<Prior Art> A flowchart type PC allows large-scale control to be described more efficiently than other programming methods such as a ladder chart type, but it has the disadvantage that it is difficult to debug programs.

Debugging of a flowchart type PC is carried out by a method called tracing. In other words, it is necessary to execute a user program and check the route through which processing progresses at a certain point on a flowchart. Therefore, in conventional flowchart type PCs, user program processing is used as a means of realizing the trace function. Execution order storage means stores in a buffer the address of each instruction executed first in the process while updating the address of the most recent execution of the plurality of steps to the first number, and compares the address of the instruction to be executed with a preset trigger address. means for detecting a match between the two, means for stopping the execution order storage means from updating the contents of the buffer after a predetermined step after the match with the trigger address is detected, and means for reading the contents of the buffer to the outside. and.

<Problems to be Solved by the Invention> According to the conventional trace function, if an arbitrary point on a flowchart (S-program) is set as the trigger address, the route before and after that point can be controlled. It is possible to know from the contents of the buffer of the execution order storage means whether the execution sequence has been executed or not. This is very useful information for all debugging efforts. However, this alone is not sufficient for debugging. Even if you understand the flow of control, there are some points (
Since the control input/output signal information and internal control information when passing through the step) are not known, efficient debugging cannot be performed.

This invention was made in view of the above-mentioned conventional problems, and in addition to the conventional trace function, the purpose of this invention is to provide all the control input/output signal information and internal control information that are considered necessary when control progresses to a certain point. We decided to provide a 70-chart type PC so that it can be collected.

Means for Solving Problems> Therefore, in the present invention, when a specific instruction set in a user program is executed, specific control input/output signal information and internal control information specified by the instruction are stored in a second buffer. A means for storing and a means for reading out the entire contents of this second buffer are added.

<Embodiment> FIG. 1 shows the overall configuration of a PC according to an embodiment of the present invention. This PC includes a CPU (arithmetic processing unit) 1 and a system program memory 2.

7 stem working memory 3, programming console 4 and 5 user program memory 5.

It includes an input circuit 6, an output circuit 7, and a data memory 8.

A number of control input signal sources are connected to the input circuit 6. The output circuit 6 has a large number of control output signals IJI/-, to which a device to be controlled is connected. In addition, in order to realize timer and counter control functions and to perform control using internal auxiliary relays, data memory 8 has a timer area, counter
area, internal auxiliary relay area, etc. are set, and these can be used arbitrarily by the user program. The contents of this data memory 8 are the aforementioned internal control information.

The control input/output signal information refers to the states of input/output signals of the input circuit 6 and the output circuit 7.

The CPU sequentially reads each instruction of a user program written in a flowchart format from the memory 5, processes it, creates a control flow according to control input/output signal states and internal control information, and as a result controls output signals and internal control information. The control information will be updated.

The programming console 4 has a human input device such as a keyboard, a display device such as a CRT, and an output device such as a printer. This console 4 is used to perform all programming/programming operations, as well as two debugging operations related to the essential parts of the present invention.

FIG. 2 is a flowchart showing an overview of the operation of the PC.

Iningill processing is performed in step 200, and step 2
At step 10, it is determined whether the operation mode setting of the console 4 is a user program execution mode or a tool service mode. In the tool service mode, the process advances to step 211 and processes various commands given from the console 4.

In the tool service mode, an arbitrary trigger address At is set, and all tone request flags are turned on or off by an input operation. In addition, an input operation is performed to insert the above-mentioned specific command at an arbitrary point in the user program.

The above specific instruction is named the trace instruction in the entire implementation series. The trace instruction is an instruction for collecting any control input/output signal information and internal control information, and consists of an operation code and an operand part. Command the information you want to collect in the 271st part of the operation.

That is, each control input/output signal is assigned an individual number (referred to as an I10 address), and one or more control input/output signals can be designated to that number. Similarly.

Any of the internal control information of the data memory 8 is designated by a memory address (or timer number, color/relay number, internal auxiliary relay number).

The entire operation of the user program execution mode in the flowchart of FIG. 2 will be explained.

If the trace request flag is currently turned off, the process proceeds from step 220 to step 221, where the instruction at address A1 specified by the program counter is read from the user program memory 8. If the instruction is not the above-mentioned trace instruction, step 222 →Proceed to 223 and execute the command. Thereafter, in step 224, the contents Ai of the program color/re are updated, and the process returns to step 220.

Therefore, if the trace request flag is off and the trace command is not set, step 220-22
1 → 222 → 223 → 224 processing? Repeat.

If the trigger address At is set and the trace request flag is on, in step 230 the instruction address Ai of the program color is stored in the buffer B1. Next, in step 231, the match flag F is set to O/"t".
Is it? judge. In the initial state, the match flag F is off "0", in which case step 232
K advance, instruction address Ai and trigger address At
Determine whether or not they match. If they do not match, the process directly advances to step 221; if they do match, the match flag Fk is set to "1" in step 233, and then the process advances to step 221K. When F=“1′, step 240
is executed.

The trace Yasugi flag is turned off here.

The buffer Bl has a capacity to store 10 instruction addresses 'fclfl, and in step 230, the latest instruction address Alf is stored in the /ft register format.
The instruction addresses for the latest 10 steps are stored here. Then, step 230 is no longer executed after l steps after Ai = At.

The contents of co-buffer B1 are preserved as is.

Next, execution of a trace instruction will be explained. A trace command is set at an arbitrary point (step) in the user program, and when the trace command is read from the user program memory 5 in step 221, the trace command is read out from the user program memory 5 in step 22.
The process proceeds from 2 to 250, and this instruction is executed at ζ. The control input/output signal information and internal control information specified in the opera/do portion of the trace instruction are stored in the buffer B2.The above processing is performed every time step 250 is executed until the buffer B2 is full.

The information stored in B7A B1 and B2 is.

By switching to the tool service mode and giving a command to read information on the console 4, it is possible to display the CRTK on the console 4 and perform grid/door operations. All program debugging is performed based on the externally outputted information in this way.

Note that the above trace command is deleted from the user program when it is no longer needed.

<Effects of the Invention> As explained in detail above, in the flowchart type PC according to the present invention, it is possible to know not only the execution path of the user program but also control input/output signal information and internal control information at a certain point in time. This greatly improves program debugging capabilities compared to conventional methods.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PC according to an embodiment of the present invention.
FIG. 2 is a flowchart showing the operation of the above PC. B1...first buffer, B2...second buffer.

Claims (1)

[Claims] In a flowchart type programmable controller that serially processes a user program written in a flowchart format along its flow, the address of each instruction that is executed sequentially in the user program processing process is updated in sequence by the number of steps of the latest execution. an execution order storage means for storing in a first buffer; a means for comparing an address of an instruction to be executed with a preset trigger address to detect a match between the two; and a predetermined step after a match with the trigger address is detected. means for later stopping the update of the contents of the first buffer by the execution order storage means, and specific control input/output signal information and internal control information specified by the specific instruction set in the user program when the instruction is executed. state storage means for storing in a second buffer;
A flowchart type programmable controller characterized by further comprising means for reading the contents of the first buffer and the second buffer to the outside.