JPH04284543A - Microcomputer program tracing device - Google Patents

Abstract

PURPOSE:To provide a microcomputer controller capable of tracing a program without changing the program and besides, without stopping the operation of equipment. CONSTITUTION:The device is constituted by adding a tracing device 9. Thus, an address can be taken out of a program ROM 2 by the latch 10 of the tracing device 9, and can be outputted from a connector 14 only at the time of a fetch cycle. Further, by the switching of a switch 13, only the designated address among the taken out addresses is selected by a gate 12 and outputted to a ROM 11 for analysis.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer control device equipped with a program tracing function.

0002

[Prior Art] Microcomputer control device (hereinafter referred to as
When equipment controlled by a microcomputer control device (called a microcomputer control device) does not operate normally, it is necessary to trace the program of the microcomputer control device and analyze whether the programs are executed in the correct order.

Conventionally, this tracing method has involved inserting a message output command to a display device such as a CRT in the middle of a program. This allows you to determine how far the program has run successfully by looking at the displayed messages.

Another method is to install an ICE (in-circuit emulator) in the module of the microcomputer control device.
Connect the ICE and use the ICE's trace function and step execution function to determine whether the program executed normally.

[0005]

[Problems to be Solved by the Invention] However, in the method of inserting a message output command in the middle of a program, in order to change the program, it is necessary to
It is necessary to rewrite the OM or download modification software from an external source, which takes a lot of effort and time. Moreover, this method cannot be used in equipment that does not have a display device such as a CRT.

[0006] Furthermore, in the method of connecting the ICE to the module, it is extremely difficult to connect the ICE probe on site due to space constraints. Moreover, the processing speed of the microcomputer control device decreases due to the connection of the ICE.

Furthermore, in any of the above methods, the operation of the equipment must be temporarily stopped in order to change the program or connect the ICE.

[0008] As a microcomputer control device having a trace function, a trace command is written in a program, thereby displaying the program contents on a display, and tracing is performed.
3504. In addition, Japanese Patent Application Laid-Open No. 60-20147 is a method for sampling the contents of a specified internal memory and performing tracing using the history of this internal memory.
is shown.

The present invention was made to solve these problems, and aims to provide a microcomputer control device that can trace a program without changing the program or stopping the operation of the equipment. purpose.

0010

[Means for Solving the Problems] A microcomputer control device according to the present invention has a trace device added thereto. The trace device includes a means for extracting an address at a fetch cycle from the address bus, a means for extracting an address of an arbitrary fetch cycle from among the extracted addresses, and a means for extracting the extracted address to the outside of the microcomputer. We are prepared.

[0011]

[Operation] By adding the above trace device, it becomes possible to output a predetermined address without changing the program, and to trace and analyze the operating state of the program.

0012

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing a first embodiment of a microcomputer control device (hereinafter referred to as a microcomputer control device) according to the present invention.

As shown in the figure, in this microcomputer control device, C
The PU 1 and the arithmetic processing program ROM 2 are connected via a buffer 3 to a data bus 4 and via a first latch 5 to an address bus 6. Further, a decoder 7 is connected to the address bus 6, and a bus controller 8 is further connected to the CPU 1 and program ROM 2.

Normally, inside a microcomputer, when the CPU retrieves an instruction from the program ROM, the CPU sends a signal specifying the address where the instruction is written to the program ROM.
The program ROM sends the instruction stored at the specified address to the CPU. This cycle in which the CPU reads instructions from the program ROM is called a fetch cycle. The CPU then executes the contents based on the instruction obtained through this fetch cycle.

These configurations are similar to those of a normal microcomputer control device, but this microcomputer control device is characterized by the addition of a trace device 9.

The trace device 9 includes a latch 10 that takes out an address from the CPU 1 through the address bus 6 only during a fetch cycle, an analysis ROM 11 that specifies an address to be output, and all data taken out by the latch 10. A gate 12 and a switch 13 select whether to output the address specified by the analysis ROM 11 or only the address designated by the analysis ROM 11, and output the address to the outside of the microcomputer control device according to the output selection by the gate 12 and switch 13. It is equipped with a connector 14 for output.

In addition, the second latch 10 of the trace device 9 is connected to the AN from the CPU 1 and the bus controller 8.
so as to give a control signal via the D circuit 15.
The analysis ROM 11 also includes the AND circuit 15 and the N
It is configured to provide a control signal through the OT circuit 16. Further, the switch 13 is connected between the analysis ROM 11 of the trace device 9 and the gate 12.
It is configured to pass a control signal through the NOT circuit 17.

Next, the operation of the microcomputer control device having the above configuration will be explained using the timing chart shown in FIG. In this timing chart, ■, ■, ■ indicate address signals, and other ■, ■, ■, ■, ■ indicate control signals at each terminal of the CPU 1, bus controller 8, latch 10, and analysis ROM 11. .

Switch 13 of trace device 9 to gate 1
2 and the analysis ROM 11 are connected through the NOT circuit 17, the latch address signal (2) taken out by the latch 10 is output from the connector 14 only when the address specified by the analysis ROM 11 is fetched.

For example, addresses n, n+1, n+2,...
If you want to output only addresses n+1 and n+3, write "01h" to addresses n+1 and n+3 of the analysis ROM 11, and write "00h" to the other addresses, as shown in FIG. put. Then, as shown in the timing chart, addresses n+1 and n
Only +3 is selected and output as the select address signal ■. For example, in a sample program as shown in Figure 4(A), if you want to output an address only when a labeled instruction is fetched,
As shown in Figure 4(B), the analysis ROM that matches the labeled address 0100, 0352, 1578
It is sufficient to write "01h" to the address No. 11 and "00h" to the other addresses.

[0022] In this way, by outputting thinned out addresses instead of addresses during all fetch cycles, a sufficient amount of time is ensured for one address to be displayed, making it easier to read the address during analysis. There is.

In this way, if the address specified in the analysis ROM 11 is retrieved from the external output connector 14 and displayed, the address of the program currently being executed inside the microcomputer can be confirmed. By sequentially checking this address, it is possible to check whether the program is being executed in the correct order. For example, if an address different from the expected address is displayed at a certain point, it can be seen that there is an error in the content of the program following the address one address before this address.

Furthermore, if the contents of the analysis ROM 11 are changed so that more detailed addresses are sent for parts of the program that have errors, it becomes possible to limit the parts of the program that have errors to a narrower range.

Furthermore, if the switch 13 of the trace device 9 is switched to the ground side and the gate 12 is grounded, all the address signals (shaded area) during the fetch cycle taken out from the address signal ■ by the latch 10 of the trace device 9. However, it is also possible to output it from the connector 14 as the latch address signal (2).

As mentioned above, in this microcomputer control device,
The tracing device 9 added as part of the configuration allows tracing, outputting, and analysis without changing the arithmetic processing program. Therefore, there is no need to stop the operation of the equipment to be controlled. Moreover, it is possible to output all addresses during a fetch cycle, or only a specified address, so you can understand the operating order of each block in the program, making it easier to analyze the program. It is possible.

FIG. 5 is a block diagram showing a second embodiment of the microcomputer control device according to the present invention. As shown in the figure, in this embodiment, a readable/writable analysis memory 21 such as an SRAM and a transceiver 22 are provided in place of the analysis ROM 11 of the trace device 9 in the first embodiment. The analysis memory 21 contains the program R
It is connected to the OM2 by an address bus 6a, and is also connected to the data bus 4a via the transceiver 22. In addition, an AND circuit 23 is added for a control signal to the analysis memory 21, and an AND circuit 24 is connected between the first latch 5 and the decoder 7, and its AN
A NOT circuit 25 is added between the D circuit 24 and the CPU 1, respectively.

By using the readable/writable analysis memory 21 in this way, it becomes possible to freely specify the address to be output from an external input/output port such as RS-232C. In addition, in the above configuration, the analysis memory 21 is chip-selected not only during the normal read/write operation but also during the fetch cycle, but at that time, the transceiver 22 becomes high impedance, so the gate can be gated without affecting the operation of the CPU 1. 12
can be controlled.

In the microcomputer control device of this second embodiment, by gradually increasing the number of specified addresses,
By narrowing down the problem areas in the program, analysis can proceed more easily.

Furthermore, as an application example of the microcomputer control device according to the present invention, as shown in the partial configuration diagram of FIG. It can be done.

That is, the program is divided into several processes 1, 2, . . . n as shown in the flowchart of FIG.
Arranged at 0h~, 0200h~, 0300~,... Then, the LED 31 is turned on to indicate the address placed at the start of each process 1, 2, . . . n.

However, if only the light is turned on at the start, the
As shown in the timing chart (A), the lighting time t
is very short and difficult to see with the naked eye. Therefore, by replacing the gate 12 of the trace device 9 with a third latch 32 as shown in the partial configuration diagram of FIG. 7(B),
As shown in FIG. 7A, the lighting time t can be extended to T, and the progress of the process can be easily confirmed visually.

[0033]

As explained above, according to the microcomputer control device of the present invention, a program can be traced without changing the program or stopping the operation of the equipment. Furthermore, since only specified addresses can be output, the operating order of the program in blocks can be grasped, and the program can be analyzed more easily.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a first embodiment of a microcomputer control device according to the present invention.

FIG. 2 is a timing chart in the first embodiment.

FIG. 3 is a diagram illustrating designation of an address to an analysis ROM in the first embodiment.

[Figure 4] (A) is a diagram showing a sample program, (B)
is a ROM for analyzing addresses in the sample program.
It is a figure explaining the designation to.

FIG. 5 is a configuration diagram showing a second embodiment of the microcomputer control device according to the present invention.

FIG. 6A is a partial configuration diagram showing an application example of the microcomputer control device according to the present invention, and FIG. 6B is a flowchart in the application example.

[Fig. 7] (A) is a timing chart in an application example;
(B) is another partial configuration diagram in the application example.

[Explanation of symbols]

1 CPU 2 Program ROM for calculation processing 9 Tracing device 10 Latch 11 Analysis ROM 12 Gate 13 Switch 14 Connector 21 Analysis memory

Claims (1)

[Claims] 1. A trace device for a microcomputer program that monitors a program operating state of the microcomputer, the trace device comprising: means for extracting an address during a fetch cycle from an address bus;
A microcomputer program tracing device comprising means for extracting an address of an arbitrary fetch cycle from among the extracted addresses, and means for extracting the extracted address to the outside of the microcomputer.