JPS5966217A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To eliminate glitch generated from a D/A converter by ANDing a signal being the result of comparison between an input signal having a prescribed slope to its edge and an output signal of the D/A converter, and the input signal. CONSTITUTION:The input signal 42 shifted to the same voltage level as that of an output signal 43 of the D/A converter 2 and waveform-shaped at a transistor (TR) 15, and the output signal 43 of the D/A converter 2 are compared at a comparator 3 and a comparator output signal 44 is obtained. A TR16 shifts the level of the input signal 42 waveform-shaped at the TR15 to the ECL logical level and applies the result to an ECL NAND gate circuit 12. The glitch included in the signal 44 is eliminated at the circuit 12, where comparator output signal 44 and the input signal 45 through the TR16 are ANDed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a variable delay circuit using a digital/analog converter (hereinafter referred to as a LK converter). □ [Prior Art] As this type of variable delay circuit, the one shown in FIG. 1 is conventionally known. 'That is, a ramp circuit l that transforms the edges of the input signal 4 into a waveform 5 with a constant slope;
A converter 2 converts data 8, which is a preset control signal, into digital/analog, a wrap circuit 117), an output signal 6, and an output signal of the D/A converter 2.
It is similar to comparison fL comparator 3.

Number '2-' shows each signal waveform of the circuit in Figure 1,
(α) is the input signal 4 to the lamp circuit l, (b) is the output signal 5 of the lamp circuit l, (C) is the D/A□ converter 2'o
Output signal 6, (d) is the delay circuit output signal F.

Figure 3 shows #W of a variable delay circuit using a variable delay circuit.
! In the signal waveform diagram shown in k, (α) is the relationship between the D/A * converter 2 output signal = z 62 and the output signal 4□2 of the lamp circuit l, and (b) □ is the relationship between the delay circuit output signal section F2. Ga'zu.
・The principle of the variable delay circuit will be explained with reference to FIG.

As shown in FIG. 3(□α)K, by inputting the output □ signal 61 and the signal 62 from the D/A converter 2 from the lamp circuit l, an output signal curve as shown in FIG. 3(b) is obtained. 1 or 72 is obtained.

As can be seen from Figure 3, the pressure bell 6 of the converter 2
Due to the difference of 1.62, the output signal of comparator 3 is 7.
1. A time difference appears in the start-up of F2, which makes the delay time variable. 'I can do that.

Next, with reference to FIG. 2, the problems of the conventional circuit shown in FIG. 1 will be explained.

As shown in Fig. 2 (C), due to the performance of the D/A converter 2, when the Σ data 8 is switched at the control key number, a glitch 9 is generated. The included output signal 6 is input to the converter 3'.
,′.

The comparator 3 is connected to the output car number of the lamp circuit shown in Fig. 2(,,,j)K.
/A converter 2 output signal 4, and compare it with the output signal 4 of the /A converter 2.
) to obtain the output signal shown in FIG. At this time, the glitch 1° is output as is, so the range of use of a variable delay circuit using a D/A converter is limited, and the delay time cannot be controlled in real time. [Purpose of the present invention] □The purpose of the present invention is to remove the blemish generated by the lux converter. The purpose is to defecate the variable delay circuit. - [□Summary of the invention] In order to achieve such an object, the present invention provides a signal that is a comparison result between an input signal whose edges have a certain slope and an output signal of a D/A converter, and ',1',.

7. Glitches are removed by performing a logical product with the input signal. There are % and 4. ,.

[Embodiments of the invention], :,.

Hereinafter, embodiments of the present invention will be described in detail as they are applied to the snow surface. ,,.

, 2nd Shizukuji, Motosakura Akira shows the configuration of one embodiment of the variable delay circuit, in which 11 indicates that the ECL gate circuit 12 is low.
CLNAND gate circuit, 13 to 1d are transistors,
17 is a capacitor, 18-', and 33 are resistors.The variable delay circuit according to the present invention mainly takes out the output at the emitter 7 lower, so the ECL can lower the output impedance.
gate, circuit 11, transistor lAl4 resistor 21-2
A constant current circuit composed of + and an input signal along with this constant current circuit.

A capacitor 1 determines the slope of the edge, and a transistor 1 makes the edge of the input signal a smooth straight line.
5, real-time controlled 1. A D/A converter 2 which performs digital/analog conversion processing on data that is a control signal, a comparator 3 which compares input signals from the transformer 2 and the control signal from the D/A converter 2, and a digital /To remove glitches that occur during analog conversion,
The ECLHAND gate circuit 12 is different from the ECLHAND gate circuit 12.
.

FIG. 5 shows the waveforms of each signal in FIG. I went through the process. Input signal 42, (d) is sent to the output signal 4 of the torque converter 2, (g) is the output signal 44h of the comparator 3, (f) input signal 4fS passed through the transistor 16, (y) is the output signal of the gate circuit 12. Output signal 46 is shown.

The operation shown in FIG. 4 will be explained below with reference to FIG.

, ζ, QA is the transistor used for the vine follower in the ECL gate circuit ll. .

The voltage of this transistor QA is high level (hereinafter referred to as
When it reaches the H level), the output is B level ξ, and the voltage is applied to the capacitor 1.7 at the speed determined by the resistor 19 and the controller f7. adK saved le 0. This charge is transferred to a transistor (2A dried honey?

Don't worry more than the voltage.　　　：、、。

Here, the base voltage E of transistor QA! Force t (Jil
Z Bell (hereinafter referred to as L level) and 44 points 1. , the base-emitter voltage of transistor QA is glu, 4
．． Baα7!・It will be less than '. Therefore, transistor QA is turned off and 1. The wealth and load stored in the capacitor 17 are set by a constant current circuit and discharged by a meridian current.
゛It will be 1.

When the discharge continues and the voltage between the base and emitter of the transistor QA increases, for example, αtVxh, the transistor QA turns on and current gradually begins to flow from the transistor QA, slowing down the rate of discharge of the charge in the capacitor 17. . Therefore, the slope of the edge of the input signal is as shown in Figure 5 (
A) is due to the signal 41.

The variable delay circuit using the D, /A converter 2 receives the input signal 4.
By adjusting the falling slope of 1, the delay time can be corrected. Well, the delay time can be easily corrected by changing the current value of the constant current circuit. Further, the 8 degrees of the variable delay circuit is determined by the linearity of the edge of the input signal 41 shown in FIG. 6(h). For this reason, the input signal 41 is made into a smooth linear waveform 42 as shown in FIG. 6(C) using the transistor 15. This transistor 15 changes the voltage level of the input signal 41 to
jE by the comparator 3, and the Luther converter 2 in FIG. 5(d)
The level is adjusted when comparing with the output signal 43 of.

The resistor 19 has the function of quickly stabilizing the output waveform 41 of the ECL gate circuit 11, and the resistor 2 (42) has the function of preventing the transistor i416 from firing.

In the D, 'A converter 2, data 41, which is a control signal, is sequentially subjected to gauge/tal/analog conversion processing under OFF/MJ control. , at this time, the D/A converter 2 generates glitches as shown in FIG. 5(d), and No. 48 including this glitch is applied to the comparator 3'. Furthermore, since the lq converter 2 is of a current source type, the voltage applied to the comparator 3 is obtained by the resistor 25.

Multi-waveform shaping is performed by the transistor 15, and the A/D converter 2
The comparator 3 compares the input signal 42 shifted to the same voltage level as the output signal 4r5 of the I/A converter 2 with the output signal 43 of the I/A converter 2, and obtains the comparator output signal 44 shown in Figure 5. .

The transistor 16 shifts the input signal 42 whose waveform has been shaped by the transistor 15 to the logic level of ECL.
Added to CLNAND gate circuit products.

In the ECLNAND gate i path 12, the comparator output signal 44 shown in FIG. 12 (-) and the input signal 8 through the transistor 16 shown in FIG. , the glitch contained in the signal 44 in FIG. 6(g) can be removed.

In the above-described embodiment, the bits of data 47 to l)/A"741 exchange rate 2 are shown as 4 bits, but this is not limited to this, and by increasing the number of bids, variable delay can be realized. You can raise the circuit disassembly bear.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate glitches that have been a problem in conventional delay circuits using D/A converters.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a conventional variable delay circuit, Fig. 2 is a waveform diagram of each signal in Fig. 1, and Fig. 3 is a signal waveform diagram showing the principle of a variable delay circuit using a Luther converter. Branch 41 A configuration diagram of an embodiment of the variable delay circuit according to the present invention, FIG.
3 is a waveform diagram of each signal in the figure. FIG. 2... Lux converter, 3... Comparator, 11.
...ECL gate circuit, 12...ECLNAND
Gate 71 1st error 4 ・3rd figure 1st error □

Claims (1)

[Claims] □A signal generation circuit that converts the changing part of the input signal into a waveform with a constant slope, a digital/analog converter that converts digital data into level signals, and an error in the output of the signal generation circuit. □ A variable delay circuit having a comparator for comparing the output of the queen comparator with the output of the signal generating circuit, characterized in that the variable delay circuit includes a logic circuit that takes a logical product of the output of the queen comparator and the output of the signal generating circuit. circuit.