JPS61156917A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To attain miniaturization by using a voltage obtained by a D/A converter at a terminal of a comparator as a reference voltage and applying reference voltages of two levels while changing their timings. CONSTITUTION:An integrated output is fed to one terminal of a comparator 7 and a reference voltage V1 is fed to the other input of the comparator 7 via a switch circuit 10 from a D/A converter 8. When the voltage from the integration circuit 6 reaches a value V1, a waveform rises from an output of the comparator 7, its output switches the switch circuit 10 and a reference voltage V2 is fed to the comparator 7 via a D/A converter 9. When an output from the integration circuit 6 decreases less than the level of the V2, the output of the comparator 7 descends and an output pulse delayed by a time t0 is obtained to the input pulse. The falling of the output pulse sets the switch 10 to the position of the D/A converter 8. Thus, the delay time is set with very high accuracy and the delay circuit is formed with small size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field of the Invention] The present invention relates to a variable delay circuit that can set an appropriate delay time.

[Problems to be solved by the present invention]

In general, variable delay circuits are constructed from a combination of a delay element constituted by an LC element and a multiplexer, and have the drawback of being large in size and expensive.

[Object of the present invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional system and provide a variable delay circuit that is small in size and relatively inexpensive. or,
To provide a variable delay circuit in which delay time can be easily set and pulse width can be easily set.

[Summary of the invention]

The variable delay circuit of the present invention outputs an integral waveform having a predetermined rise time and fall time by passing an input pulse through an integrating circuit, and supplies the output of this integral waveform to one input terminal of a comparator. By using the voltage obtained by the D/A converter as a reference voltage to the other terminal of the comparator, the D/A converter supplies two levels of reference voltage at different timings, thereby providing a predetermined response to the human pulse. It is characterized by obtaining an output pulse having a delay time of 1 and a predetermined pulse width. The reference voltage may be set by supplying it from two switched D/A converters based on an external control signal.

[Example of the present invention]

The variable delay circuit of the present invention will be explained based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a variable delay circuit according to the present invention. The embodiment shown in FIG. 1 is composed of a buffer circuit 5, an integration circuit 6, a comparator 7, D/A converters 8 and 9, and a switch circuit 10.

1 is a terminal to which an input pulse is supplied, and 2 is a terminal from which an output pulse delayed by a predetermined time with respect to the manual pulse is obtained. 3 and 4 are input terminals to which external control signals (digital signals) are supplied.

The square wave pulse input to the terminal l is sent to the buffer circuit 5.
The signal is supplied to an integrating circuit 6 formed from a resistor, a capacitor, etc., through which an integrated waveform output is obtained.

One terminal of the comparator 7 is supplied with the output from the integrating circuit 6, and the other terminal of the comparator 7 is supplied with a predetermined reference voltage set by the D/A converter 8.9 via the switch circuit 10. E, l are supplied. For the reference voltage ER, an external control signal in the form of a digital signal is supplied to the D/A converters 8 and 9 via the terminals 3 and 4, and reference voltages V, . . . V2 having predetermined values are obtained. The reference voltages obtained from the D/A converters 8 and 9 can have good linearity by adjusting the number of steps of the external control signal. switch circuit 1
0, the reference voltage v1 is initially supplied to the comparator 7 via the D/A converter 8, but the electric line 11 from the output terminal of the comparator 7
is controlled through the switch circuit 10 to switch the D
The reference voltage V2 is supplied to the comparator 7 via the /A converter 9.

Now, the operation of the variable delay circuit of the present invention will be explained with reference to FIG.

A square wave pulse as shown in FIG. 2(a) is input to the terminal 1, and is processed by the integrating circuit 6 with a predetermined time constant as shown in FIG. 2(b) with rise times t, l and fall time 1. This integrated output is supplied to one terminal of the comparator 7. Since the reference voltage vl is supplied from the D/A converter 8 to the other terminal of the comparator 7 via the switch circuit 10, when the voltage from the integrating circuit 6 reaches the value of A waveform rises from the output terminal as shown in FIG. 2(C), and this output switches the switch circuit 10 and switches the D/A
A reference voltage (2) is supplied to the comparator 7 via the converter 9.

Further, when the output from the integrating circuit 6 falls below the level of the reference voltage V2, the output from the comparator 7 falls, and the time t with respect to the input pulse. It is possible to obtain output pulses that are delayed by a certain amount.

As this output pulse falls, the switch 10 is switched to the D/A converter 8 side. Also, the reference voltage V,,V
The relationship between the two potentials is set to V>V2. V, <V2
When setting the relationship, the rise time t of the integral waveform
It is necessary to apply a lunch so that comparator 7 does not operate at R. In this way, the delay time tD and pulse width are
It can be set appropriately by adjusting the time constant of the integrating circuit 6 and the reference voltage of the D/A converter 8.9.

FIG. 3 is a circuit diagram showing another embodiment of the variable delay circuit of the present invention. The difference from the embodiment shown in FIG. 1 is that the reference voltages E and l supplied to the comparator 7 are obtained by one D/A converter 12. The D/A converter 12 is supplied with a control signal (digital signal) from a control signal generation circuit 13 for obtaining two levels of reference voltage. The timing of switching the control signals may be determined by the same method as in the embodiment shown in FIG. A clock pulse is supplied from terminal 14. Further, the control signal generation circuit 13 may set the control signal using a switch.

[Effects of the present invention]

As described above, the variable delay circuit of the present invention includes an integrating circuit that processes input pulses, a D/A converter that generates two levels of reference voltage, and an input signal that compares the reference voltage and the output from the integrating circuit. It consists of a comparator that obtains an output pulse that is delayed with respect to the pulse, and a control section that switches the reference voltage.The time constant of the integrating circuit can be easily set, and two levels of reference voltage can be set using an external signal. Since it can be easily set using a D/A converter, it has the advantage that it is possible to set the delay time with extremely high accuracy, and it is also possible to obtain an output pulse having an arbitrary pulse width.

Furthermore, since the variable delay circuit of the present invention can be formed by a semi-contaminated integrated circuit or a hybrid circuit, it has the advantage that it can be formed compactly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the variable delay circuit according to the present invention, and FIGS. 2(a) to (C) are timing charts for explaining its operation. FIG. 3 is a block diagram showing another embodiment of the variable delay circuit according to the present invention. 5: Basofa circuit, 6: Integrating circuit, 7: Comparator 8.9.
12: D/A converter 10: Swiss circuit 13: Control signal generation circuit

Claims (3)

[Claims] (1) Obtain the output of an integral waveform having a predetermined rise time and fall time by passing the input pulse through an integrating circuit,
The output of this integrated waveform is supplied to one input terminal of a comparator, the voltage obtained by a D/A converter is supplied as a reference voltage to the other terminal of the comparator, and the level of the reference voltage is switched. , a variable delay circuit that sets the delay time and pulse width of the output pulse from the comparator. (2) The variable delay circuit includes an integrating circuit that integrates square wave pulses, first and second D/A converters that can set arbitrary reference voltages based on an external control signal, and 1 and a switch circuit for switching the reference voltage from the second D/A converter, and a comparator to which the output from the integrating circuit and the reference voltage selected by the switch circuit are supplied, and from the comparison The switch circuit is operated by the output of the comparator, and the reference voltage supplied to the input terminal of the comparator is switched, thereby obtaining an output pulse having a predetermined delay time with respect to the input pulse from the comparator. A variable delay circuit according to claim 1. (3) The variable delay circuit includes an integrating circuit that integrates square wave pulses, one D/A converter that can set an arbitrary reference voltage based on an external control signal, and the D/A converter. 2. The variable delay circuit according to claim 1, further comprising means for switching the control signal supplied to the comparator according to the output from the comparator.