JP6641421B2 - PWM duty cycle synthesizer and method with adjustable corner frequency - Google Patents

Description

  The present invention relates generally to a PWM circuit that generates a PWM output signal in response to a PWM (pulse width modulation) input signal, and more particularly to a fixed frequency and a duty cycle that is the same as the duty cycle of the PWM input signal. And a PWM output signal that generates a PWM output signal having the following.

PWM circuits are widely used as control circuits, particularly in electric motor drive applications. The PWM output signal is typically generated by digital circuitry and associated system clock signals, or by analog comparator circuitry. For a typical brushless DC (BLDC) motor controller, the system clock f _sys ranges from approximately 1 MHz to 10 MHz, and the expected output PWM frequency f _PWM ranges from approximately 20 kHz to 200 kHz, depending on the specific application. It is.

  One prior art PWM motor drive circuit includes a specially designed PWM generator, an output multiplexer (MUX), and an interpolator to increase duty cycle resolution (the term "duty cycle resolution" Refers to the minimum allowable increment or change in duty cycle, eg, a digital system may calculate or provide a 4% or 5% output duty cycle, but any fractional duty cycle between 4% and 5% If the resolution cannot be calculated or provided, the duty cycle resolution of this system is 1%). Another prior art technique for increasing duty cycle resolution is to convert the duty cycle from PWM to a DC value using an RC filter and to convert the DC value of the duty cycle to a digital representation using an ADC (analog to digital converter). Thus, a PWM output signal having exactly the same duty cycle and exactly the same desired frequency is digitally generated. Yet another known method uses a counter to determine a positive duty cycle duration, divides it by the overall duty cycle to determine a duty cycle, and uses that information to generate a PWM output signal. .

Some users of motor driver circuits may prefer to provide relatively low PWM input signal frequencies ranging from approximately 2 kilohertz to as high as approximately 100 kHz or higher. The user provided PWM input signal is typically applied directly to the motor drive circuit. Motor driver integrated circuits may require that the motor drive PWM frequency be particularly fixed, but in some cases it may not be suitable for the user. Rather, some users desire that the motor drive PWM frequency be independent of the frequency of the PWM input signal provided by the user. Some conventional PWM circuits can satisfy this requirement. For example, Re counter et used to identify a positive pulse width and overall pulse width of the PWM input signal obtained, resulting divider is used to identify the duty cycle signal, the duty cycle signal PWM generator Used by the circuit to generate a PWM output signal.

  In a typical motor system, PWM pulse width variations between cycles can be filtered out by the physical rotor momentum, which can be viewed as a low pass filter system. However, in many instances, a user may prefer to use a low frequency PWM input signal to control the motor drive circuit, but unfortunately, the low frequency PWM signal generally drives the electric motor. Not suitable for Rather, many users may prefer a corresponding, substantially higher frequency, PWM output signal to drive the motor. Where the PWM input signal has a relatively low frequency, substantially higher frequencies of the PWM output signal are typically achieved by using the counter and divider approach described above. Some conventional circuits require the input PWM frequency to be within a certain range, and some conventional circuits use a counter and divider converter as described above. Usually, it is preferable that the frequency of the PWM motor drive signal does not depend on the frequency of the PWM control signal supplied by the user.

  In many cases, neither an excessively sharp increase nor an excessively sharp decrease is desirable for the motor speed controlled by the motor driver integrated circuit. With a sudden increase in duty cycle, the motor typically accelerates under full power applications. This draws a large amount of current from the power supply, which can cause a sharp, large and unacceptable power supply voltage drop. Conversely, when there is a sudden decrease in duty cycle, the motor typically slows down by vigorously "braking" the motor. Such strong braking converts the mechanical energy of the rotor into electrical energy, which is rapidly "dumped" to the power supply. Excessive energy dumping into the power supply can cause large spikes in the power supply voltage (eg, 5-10 volts), which can damage other circuits / devices in the system.

  Thus, a PWM circuit capable of generating a PWM output signal having an output frequency independent of a user-supplied PWM input signal frequency, wherein the duty cycle of the PWM output signal is exactly equal to the duty cycle of the PWM input signal. There is an unmet need for PWM circuits.

  A PWM circuit capable of generating a PWM output signal of a relatively high frequency in response to a PWM input signal of a relatively low frequency independent of a frequency of a PWM control signal of a user, the PWM circuit comprising a PWM output signal of a high frequency There is an unmet need for PWM circuits where the duty cycle of the PWM circuit is exactly equal to the duty cycle of the low frequency PWM input signal.

  A PWM circuit capable of generating a PWM output signal of a relatively high frequency in response to a PWM input signal of a relatively low frequency independent of a frequency of a PWM control signal of a user, the PWM circuit comprising a PWM output signal of a high frequency Unsatisfactory for a PWM circuit whose programmable duty cycle is exactly equal to the duty cycle of the low frequency PWM input signal and has at least as much resolution as the duty cycle of the low frequency PWM input signal There is demand.

  Also, abrupt transfer of energy between the power supply and the PWM control electric motor due to a duty cycle difference between the PWM input signal and a duty cycle of the PWM output signal generated in response to the PWM input signal. There is an unmet need for a PWM duty cycle synthesizer circuit that can prevent occurrences.

  Also, an unsatisfied PWM duty cycle synthesizer circuit that can protect the motor from sudden occurrence of sudden acceleration or deceleration of rotation of the motor due to duty cycle mismatch between the PWM input signal and the PWM output signal. There is demand.

  A PWM circuit capable of generating a PWM output signal having a first frequency in response to a PWM input signal having a second frequency independent of a frequency of a PWM control signal supplied by a user. There is an unmet need for PWM circuits where the duty cycle is exactly equal to the duty cycle of the PWM input signal and the response time of the PWM circuit to a step change in duty cycle is programmable.

  A PWM circuit capable of generating a PWM output signal having a first frequency in response to a PWM input signal having a second frequency independent of a frequency of a PWM control signal supplied by a user. There is an unmet need for PWM circuits where the duty cycle is exactly equal to the duty cycle of the PWM input signal and the PWM circuit can be implemented in an integrated circuit chip area that is substantially smaller than the state of the art prior art.

  An object of the present invention is a PWM circuit capable of generating a PWM output signal having an output frequency independent of a user-supplied PWM input signal frequency, wherein the duty cycle of the PWM output signal is equal to the duty cycle of the PWM input signal. To provide a PWM circuit that is exactly equal to

  Another object of the present invention is a PWM circuit that can generate a relatively high frequency PWM output signal in response to a relatively low frequency PWM input signal that is independent of the user's PWM control signal. The object is to provide a PWM circuit in which the duty cycle of the frequency PWM output signal is kept exactly equal to the duty cycle of the low frequency PWM input signal.

  Another object of the present invention is a PWM circuit capable of generating a relatively high frequency PWM output signal in response to a relatively low frequency PWM input signal that is independent of the frequency of a user supplied PWM control signal. Wherein the duty cycle of the high frequency PWM output signal is programmable, exactly equal to the duty cycle of the low frequency PWM input signal, and has at least as much resolution as the duty cycle of the low frequency PWM input signal. To provide a PWM circuit.

  Another object of the present invention is to provide a method for controlling a power supply between a power supply and a PWM control electric motor due to a duty cycle difference between the PWM input signal and a duty cycle of a PWM output signal generated in response to the PWM input signal. An object of the present invention is to provide a PWM duty cycle synthesizer circuit capable of preventing occurrence of a sudden transfer of energy.

  Another object of the present invention is a PWM duty cycle synthesizer circuit that can protect a motor from sudden occurrence of sudden acceleration or deceleration of rotation of the motor due to duty cycle mismatch between the PWM input signal and the PWM output signal. It is to provide.

  Another object of the present invention is a PWM circuit capable of generating a PWM output signal having a first frequency in response to a PWM input signal having a second frequency that is independent of a user supplied PWM control signal frequency. Thus, a PWM circuit is provided in which the duty cycle of the PWM output signal is exactly equal to the duty cycle of the PWM input signal and the response time of the PWM circuit to step changes in the duty cycle is programmable.

  Another object of the present invention is a PWM circuit capable of generating a PWM output signal having a first frequency in response to a PWM input signal having a second frequency that is independent of a user supplied PWM control signal frequency. Thus, it is an object of the present invention to provide a PWM circuit in which the duty cycle of the PWM output signal is exactly equal to the duty cycle of the PWM input signal and the PWM circuit can be implemented in an integrated circuit chip area substantially smaller than the state of the art.

Briefly and in accordance with one embodiment, the present invention provides a PWM output signal (PWM _OUT ) having an output frequency (f _PWM ) in response to a PWM input signal (PWM _IN ) having an input frequency (f _PWMIN ). Is provided. The PWM circuit compares the PWM output signal with the PWM input signal, and generates an increment signal (INC) if the value of the PWM input signal exceeds a corresponding value of the PWM output signal, and An algebraic addition circuit (3) for generating a decrement signal (DEC) when the value of the signal is smaller than the corresponding value of the PWM output signal. An integrator (5) increases the value of the duty cycle signal (Duty [7: 0]) in response to each increment signal generated by the algebraic addition circuit, and in response to each decrement signal. By reducing the value of the duty cycle signal, a duty cycle signal (Duty [7: 0]) representing the duty cycle of the PWM input signal is generated. The PWM generator circuit (9) is responsive to the duty cycle signal to generate the PWM output signal such that the duty cycle of the PWM output signal is exactly equal to the duty cycle of the PWM input signal without compromising the duty cycle resolution. Generate.

In one embodiment, the invention is _responsive to a PWM input signal (PWM _IN ) having an input frequency (f _PWMMIN ) such that the duty cycle of the PWM output signal is exactly equal to the duty cycle of the PWM input signal. A PWM (pulse width modulation) circuit (1A) for generating a PWM output signal (PWM _OUT ) having an output frequency (f _PWM ) is provided. Algebraic summing circuit (3) is, PWM input signal value of _{(PWM IN)} generates an increment signal (INC) if more than a corresponding value of the PWM output signal _{(PWM OUT),} PWM input signal _{(PWM IN)} Is smaller than the corresponding value of the PWM output signal (PWM _OUT ), a decrement signal (DEC) is generated. An integrator (5) increasing the value of the first duty cycle signal (Duty [7: 0]) in response to each increment signal (INC) generated by the algebraic addition circuit (3); And reducing the value of the first duty cycle signal (Duty [7: 0]) in response to each decrement signal (DEC) generated by the algebraic addition circuit (3), thereby reducing the PWM input signal (Duty [7: 0]). A first duty cycle signal (Duty [7: 0]) representing the duty cycle of PWM _IN ) is generated. A PWM generator circuit (9) generates a PWM output signal (PWM _OUT ) in response to the first duty cycle signal (Duty [7: 0]). The PWM generator circuit (9) operates to bring the duty cycle of the PWM output signal (PWM _OUT ) closer to and substantially equal to the duty cycle of the first PWM signal (PWM _IN ).

The algebraic addition circuit (3), the integrator circuit (5), and the PWM generator circuit (9) convert the duty cycle of the PWM output signal (PWM _OUT ) into the PWM input signal (PWM _IN ) without impairing the duty cycle resolution. Form a digital feedback loop that operates to equal the duty cycle of

In one embodiment, the output frequency (f _PWM ) is substantially greater than the input frequency (f _PWMMIN ). In one embodiment, the integration circuit (5) is a digital circuit that includes an up / down counter (5), the up / down counter (5) having a first input coupled to receive an increment signal (INC). , And a second input coupled to receive a decrement signal (DEC). The algebraic addition circuit (3) generates either the increment signal (INC) or the decrement signal (DEC) when the duty cycle of the PWM output signal (PWM _OUT ) is equal to the duty cycle of the PWM input signal (PWM _IN ). do not do.

In one embodiment, the algebraic addition circuit (3) is a digital circuit including a first inversion circuit (22), which is coupled to receive a PWM output signal (PWM _OUT ). Has the input entered. A first logical AND circuit (25) has a first input coupled to receive a PWM output signal (PWM _OUT ). A second inverting circuit (24) has an input coupled to receive a PWM input signal (PWM _IN ). A second logical AND circuit (23) has a first input coupled to receive a PWM input signal (PWM _IN ). A second input of the first logical AND circuit (25) is coupled to an output of the second inverting circuit (24), and a second input of the second logical AND circuit (23) is connected to the first inverting circuit (23). Coupled to receive the output of the circuit (22). The first logical AND circuit (25) and the second logical AND circuit (23) generate an increment signal (INC) and a decrement signal (DEC), respectively.

In one embodiment, PWM generator circuit (9), the system clock signal and the ramp generator circuit for generating a ramp signal _{(V RAMP)} in response to _{(f sys)} (33), the ramp signal _{(V RAMP} ) With a first duty cycle signal (Duty [7: 0] or GenDuty [5: 0]) and a comparator (37) for generating a PWM output signal (PWM _OUT ) accordingly. In one embodiment, the ramp generator circuit (33) generates a digital representation of the ramp signal ( _VRAMP ) and the comparator (37) is a digital comparator.

  In one embodiment, the PWM circuit includes an interpolator for generating a second duty cycle signal (GenDuty [5: 0]) that is an interpolated representation of the first duty cycle signal (Duty [7: 0]). It includes a circuit element (7). In one embodiment, the PWM generator circuit (9A) generates a plurality of PWM signals (18) having the same frequency but different duty cycles, and the interpolator element (7A) provides for an average duty cycle. Selecting a predetermined pattern of the plurality of PWM signals according to the requested PWM duty cycle, and the interpolation circuit element (7A) selects a predetermined pattern of the plurality of PWM signals by the output multiplexer (20).

In one embodiment, the invention is a method for generating a PWM output signal (PWM _OUT ) having an output frequency (f _PWM ) in response to a PWM input signal (PWM _IN ) having an input frequency (f _PWMIN ). I will provide a. The method includes generating an incremental signal (INC) when the value of the PWM input signal _{(PWM IN)} exceeds the corresponding value of the PWM output signal _{(PWM OUT),} and the value of the PWM input signal _{(PWM IN)} Generating a decrement signal (DEC) if less than a corresponding value of the PWM output signal (PWM _OUT ); and a first duty cycle signal (Duty [7: 0]) in response to each increment signal (INC). ), And by decreasing the value of the first duty cycle signal (Duty [7: 0]) in response to each decrement signal (DEC), the PWM input signal (PWM _IN ). Generating a first duty cycle signal (Duty [7: 0]) representing the duty cycle of the first duty cycle and the PWM generator circuit (5). Generating a PWM output signal (PWM _OUT ) in response to the cycle signal (Duty [7: 0]).

In one embodiment, the method includes comparing the PWM output signal (PWM _OUT ) with the PWM input signal (PWM _IN ) by a digital algebraic addition circuit (3).

  In one embodiment, the method generates a first duty cycle signal (Duty [7: 0]) by operating an up / down counter in response to an increment (INC) and decrement (DEC) signal. Including doing.

In one embodiment, the method includes generating a second duty cycle signal (GenDuty [5: 0]) that is an interpolated representation of the first duty cycle signal (Duty [7: 0]). , Step (c) includes generating, by the PWM generator circuit (5), a PWM output signal (PWM _OUT ) in response to the second duty cycle signal (GenDuty [5: 0]).

In one embodiment, the present invention provides a PWM circuit for generating a PWM output signal (PWM _OUT ) having an output frequency (f _PWM ) in response to a PWM input signal (PWM _IN ) having an input frequency (f _PWMIN ). I will provide a. This PWM circuit compares the PWM output signal (PWM _OUT ) with the PWM input signal (PWM _IN ) and when the value of the PWM input signal (PWM _IN ) exceeds the corresponding value of the PWM output signal (PWM _OUT ). Means for generating an increment signal (INC) and a decrement signal (DEC) when the value of the PWM input signal (PWM _IN ) is smaller than the corresponding value of the PWM output signal (PWM _OUT ). 3) by increasing the value of the duty cycle signal (Duty [7: 0]) in response to each increment signal (INC) generated by the algebraic addition circuit (3), and by increasing each decrement signal (DEC) ) duty cycle signal in response to the (duty [7: 0] value by decreasing the), the duty cycle of the PWM input signal _{(PWM iN)} Means (5) for generating a representative duty cycle signal (Duty [7: 0]), and a PWM output signal in response to the duty cycle signal (Duty [7: 0]) by a PWM generator circuit (5). Means (9) for generating (PWM _OUT ).

FIG. 3 is a block diagram of a PWM circuit that generates a PWM output signal having an output frequency independent of the input frequency of the PWM input signal and having the same duty cycle as the PWM input signal.

2 shows waveforms of PWM _IN , PWM _OUT , and an integrator output signal of FIG.

2 shows waveforms of a PWM _IN duty cycle, a PWM _OUT duty cycle, and a Duty [7: 0] duty cycle control signal of FIG. 1.

FIG. 2 is a block diagram of a known signal comparison circuit and a known integrator circuit element that may be used in blocks 3 and 5, respectively, of FIG.

4B shows a preferred digital implementation of block 5 of FIG. 4A.

FIG. 2 is a block diagram of known PWM generator circuitry including an interpolator and an output multiplexer that may be used in block 15 of FIG.

FIG. 4 is a block diagram of another conventional technique for generating a PWM output signal.

FIG. 2 is a block diagram of a conventional PWM generator that can be used in block 9 of FIG.

  The present invention provides a PWM control circuit that includes a duty cycle synthesizer circuit that controls the frequency of a PWM output signal (such as a PWM signal for driving an electric motor) that is independent of the frequency of a user-supplied input PWM input signal. Virtually any duty cycle difference between the PWM input signal and the PWM output signal is sufficiently filtered or smoothed to prevent excessively sharp acceleration or deceleration in the motor, so that the power supply and PWM control Any large and rapid energy exchange with the motor controlled by the circuit is prevented.

FIG. 1 shows a block diagram of a PWM control circuit 1 that can generate a PWM output signal PWM _OUT having a frequency f _PWM that is substantially _independent of a user-supplied PWM input signal PWM _IN having a frequency f _PWMIN . The PWM control circuit 1 includes a digital duty cycle synthesizer circuit 1A, which includes a signal comparison or "delta" circuit 3, an integrator 6, an interpolator 7, and a PWM generator circuit 9. (The term "delta" is used, preferably because a sigma-delta topology circuit element is used.) The delta circuit 3 has a (+) input that receives PWM _IN , and a (-) input that receives PWM _OUT as a feedback signal. . Delta circuit 3, if the _{PWM IN} is greater than _{PWM OUT,} and generates a "incremental" or "+1" signal INC on conductor 4A, when _{PWM IN} is _{PWM OUT} smaller than the conductor 4B "decrement" or "- 1 "Generate a signal DEC. If PWM _IN is equal to PWM _OUT , the delta circuit 3 does not generate either an increment signal or a decrement signal. The following truth table illustrates this operation.
An increment conductor 4A and a decrement conductor 4B are connected to corresponding inputs of a digital integrator 5, which can be implemented as a conventional up / down counter.

In the example of FIG. 1, the integrator 5 can be a 22-bit up / down counter. The eight most significant bits are received as the integrator output signal Duty [7: 0]. The output signal Duty [7: 0] of integrator 5 is generated on bus 6, which includes an optional digital interpolator 7 having an input coupled to receive Duty [7: 0]. Interpolation and PWM generator circuit "15. Interpolation and PWM generator circuit 15, a PWM input signal _{PWM IN} having the required duty cycle has the different frequencies into a PWM output signal _{PWM OUT} having exactly the same duty cycle and _{PWM IN} A _{PWM IN} , Can be considered a single circuit.

The interpolation circuit 7 generates a 5-bit digital output signal GenDuty [5: 0] on the digital bus 8. Also, the interpolation and PWM generator circuit 15 includes a conventional PWM generator 9 having an input connected to the digital bus 8 to receive the interpolated duty cycle signal GenDuty [5: 0]. In response, the PWM generator 9 generates a PWM _OUT on the digital bus 10 and feeds back the PWM _OUT to the (-) input of the delta circuit 3, thereby effectively adjusting the time constant or corner frequency. To form a negative digital feedback loop. In this example, the signal GenDuty [5: 0] on the bus 8 has two less bits than the duty cycle resolution signal Duty [7: 0] on the bus 6, and the extra two bits are the increased duty cycle resolution. Is used for interpolation to achieve The digital bus 10 is connected to an input of a conventional motor drive circuit 11, and an output of the motor drive circuit 11 controls an electric motor 12. Note that the output frequency is designed at a fixed point according to the requirements of the system in which the PWM control circuit 1 is used, and the PWM input frequency can be either lower or higher than the PWM output frequency, but the output duty cycle is equal to the input duty cycle. Note that is kept exactly equal to

The signal Duty [7: 0] is extracted from the 22-bit output of the up / down counter 5 at any particular point in time and represents the duty cycle of PWM _IN . Signals GenDuty [5: 0] represent and control the duty cycle of PWM _OUT at that time. The duty cycle difference between PWM _IN and PWM _OUT is determined by the delta circuit 3, and if there is a practical duty cycle difference, it is converted to either the above-described increment signal INC or the decrement signal DEC. (In a manner specified by probabilistic table by relating the duty cycle difference. The basic idea is, the output of the delta circuit 3 during difference between _{PWM IN} and _{PWM OUT} between the _{PWM IN} and _{PWM OUT} When the duty cycle difference to be sampled is randomly sampled, the likelihood that a "1" will be sampled is that it is the same as the duty cycle of PWM _IN . If, then, if random sampling of these two signals continues, the probability difference is the same as the duty cycle difference.)

Thus, during any time interval when the PWM input duty cycle is greater than the PWM output duty cycle, the number of increment (+1) signals will exceed the number of decrement (-1) signals, resulting in an integrator (up) / Down counter) 5 continues to increase. Conversely, during any interval in which the PWM input duty cycle is less than the PWM output duty cycle, the number of increment signals is less than the number of decrement signals, so that the output of up / down integrator counter 5 continues to decrease. . During any interval where the duty cycle of PWM _IN is equal to the duty cycle of PWM _OUT , the number of incremental signals will be equal to the number of decrement signals, so that the output of integrator 5 will not change. If PWM _IN and PWM _OUT have the same duty cycle but a different frequency over a suitably long time interval, then over that time interval the number of incrementing and decrementing pulses will be equal, and PWM _IN and PWM _IN will be equal. The duty cycle of PWM _OUT is considered "balanced".

When the feedback loop is set, ie, when there is no duty cycle difference between the input PWM signal and the output PWM signal, the “extracted” output value Duty [7: 0] generated by the up / down counter 5. Represents the duty cycle of the PWM input signal. The signal Duty [7: 0] is also a control signal for the PWM generator 9 that converts the interpolated output signal GenDuty [5: 0] to a PWMOUT signal. The input and output PWM signals have the same duty cycle, and since the 8-bit duty signal Duty [7: 0] controls the output duty cycle, Duty [7: 0] is the required input duty of the PWM control circuit 1. It represents both the cycle and the output duty cycle. The feedback loop operates to keep the duty cycle of PWM _IN and PWM _OUT tightly balanced. That is, when the feedback loop is "saturated", the desired balance or balance has been achieved between the PWM _IN and PWM _OUT duty cycles.

It should be understood that the interpolator 7 of FIG. 1 may, but need not always, be used to increase the duty cycle resolution of PWM _OUT . In some examples, the output of up / down counter 5 may be fed directly to the input of PWM generator 9 (and filtering of the negative feedback loop may still be beneficial).

The transfer function of the duty cycle of PWM _OUT can be expressed by the following equation.
_{H (s) = {A 1} · A 2 · (1 / s)} / [1+ {A 1 · A 2 · (1 / s)}]
= 1 / [1+ {s / (A ₁ · A ₂ )}]
This equation, the difference or mismatch between the duty cycle of the _{PWM IN} and _{PWM OUT} have shown that it is integrated by the sampling gain factor _{A 1.} The sampling gain factor A ₁ can be adjusted by controlling the sampling clock frequency f _sys , which is not correlated with the frequency of PWM _IN . Integrator using a 8MSB bit 22-bit output of the (up / down counter) 5 is equivalent to dividing the up / down counter output on another gain factor A _2. The duty cycle mismatch transfer function described above indicates that the negative feedback loop is a first order low pass system. The term 1 / s is a transfer function of the integrator 5. Adjusting the gain factor A ₂ is obtained by changing the response time and thus, may alter the corner frequency associated with the duty cycle mismatch transmission function.

The ratio of the up / down integrator counter "extracted" with respect to the output of the number of bits 22 integrator output number of bits 8 is equal to the gain factor A _2. A ₂ is, for example, to provide an up / down counter as a 20-bit counter, further by extracting 8MSP bits to represent the duty cycle of the _{PWM IN,} it may be adjusted. This will reduce the time constant of the transfer function described above. The term A ₁ × A ₂ controls the time constant of the feedback loop and thus also the corner frequency of the low-pass filtering function. Sampling gain factor _{A 1} is controlled by the system clock frequency _{f sys.}

FIG. 2 includes the waveforms of PWM _IN , PWM _OUT , and the 22-bit output generated by the up / down counter 5. The PWM _IN waveform has a relatively low frequency, the PWM _OUT waveform has a substantially higher frequency, and has a duty cycle that is "unbalanced" with the PWM _IN duty cycle. From the example of FIG. 2, the value of the output of the up / down counter 5 has decreased after one cycle of PWM _IN by comparing the output value of the 22-bit integrator / counter 5 at the beginning and end of the cycle. You can see that. The integrator / counter output value continues to decrease until it reaches a balanced value, effectively smoothing or equalizing the duty cycle of PWM _IN and PWM _OUT .

This substantially eliminates the problem of large and sharp acceleration and / or deceleration of the driven motor due to the difference between the duty cycles of PWM _IN and PWM _OUT described above, and thus the associated motor deceleration. the problem of dumping the energy is associates to the power supply system, and also to solve problems that result in potentially harmful spikes in the supply voltage.

FIG. 3 shows waveforms of the signals “PWM _IN duty cycle”, “PWM _OUT duty cycle”, and the integrator output Duty [7: 0]. Abrupt steps increase in _{PWM IN} at time indicated by "A", to generate a step response of the signal _{"PWM IN} duty cycle" which represents the duty cycle of the _{PWM IN.} The step response of the _{"PWM IN} duty cycle" corresponds to the count of the up / down counter 5, to produce a _{"PWM OUT} duty cycle" waveform representing the duty cycle of the _{"PWM OUT".} For the limited resolution, i.e., the number of bits that may be used to adjust the "PWM _OUT duty cycle" is limited, "PWM _OUT Duty Cycle" waveform appears as a sequence of increasing small step, typically It has an appearance similar to that of a typical RC (register-capacitor) circuit response. As such, the "PWM _OUT duty cycle" waveform follows the "PWM _IN duty cycle" waveform in a manner similar to RC circuit response with characteristic time constants and corresponding corner frequencies. That is, the signal "PWM _IN Duty Cycle" can be filtered and the associated time constant calculated. Further, the time constant and corner frequency can be adjusted or programmed by changing circuit parameters, as described above.

Low-pass filtering is achieved by the operation of the aforementioned negative digital feedback loop of the PWM duty cycle synthesizer circuit 1. This loop includes an integrator / counter 5 that contributes much of the filtering. Duty [7: 0] characteristic indicated by the response waveform and "PWM _OUT duty cycle" waveform has a constant and corner frequency when used associates, they are to be suitable for driving the various motors It can be adjusted or programmed. The programmable low-pass filtering function prevents the sudden deceleration or any particular braking, and thereby converts the mechanical energy of the electric motor into electrical energy that is quickly dumped to the power supply. It can be set to prevent.

FIGS. 4A, 4B, 5 and 6 described below are used in prior art PWM duty cycle synthesizer circuits and known circuit elements that can be used to implement the various blocks shown in FIG. The details are shown below. Referring to FIG. 4A, a simple conventional implementation of delta circuit 3 is shown, which includes an inverter 22 having an input connected to receive PWM _OUT . The output of inverter 22 is connected to one input of AND gate 23, and the output of AND gate 23 is connected to increment conductor 4A. The other input of AND gate 23 is connected to receive PWM _IN . Another inverter 24 has an input connected to receive PWM _IN , and an output connected to one input of AND gate 25. Another input of AND gate 25 is connected to receive the PWM _0UT, and the output of AND gate 25 is connected to decrement conductor 4B.

  FIG. 4A also includes an integrator 5, which may be an up / down counter as described above, or an analog integrator. FIG. 4B shows a conventional up / down counter 5A that can be used as an implementation of the integrator 5. The increment input INC of the up / down counter 5A is connected to receive the increment signal generated on conductor 4A by AND gate 23, and the decrement input DEC of up / down counter 5A is connected on conductor 4B by AND gate 25. Is connected to receive the generated decrement signal.

FIG. 5 shows a block diagram of one implementation of the interpolation and PWM generator circuit 15 of FIG. 1, wherein the interpolation and PWM generator circuit 15 is a conventional circuit clocked by a system reference clock on a conductor 17 having a frequency f _sys . It includes a PWM generator circuit 9. The digital output signal generated by the conventional PWM generator circuit 9A is generated on the digital bus 18 and includes a number of PWM signals having the same frequency but different duty cycle ranges. The signals on bus 18 are internal signals. The signal on conductor 10 of FIG. 5 is the same as PWM _{OUT of} FIG. 1 and can be fed back to the (-) input of delta circuit 3 of FIG. Bus 18 is coupled to a set of inputs of output multiplexer 20, which may be a conventional multiplexer. Also. The interpolator and PWM generator circuit 15 of FIG. 5 includes an interpolator 7A as shown in FIG.

The Duty [7: 0] signals on bus 6 represent various different duty cycles of the PWM _OUT signal generated on bus 10 by PWM generator 9A and the PWM signal generated on conductor 10 by output multiplexer 20. Control. The input of the interpolator 7A receives the two bits [1: 0] of Duty [7: 0] on the bus 6 from the up / down counter 5 and the other bits [7: 2] of Duty [7: 0]. Is provided as an input to the PWM generator 9A to identify PWM signals having different duty cycles generated on the internal bus 18. Interpolator 7A controls which of the different duty cycle PWM signals on bus 18 are multiplexed onto conductor 10. When the feedback loop is stable, the duty cycle of PWM _OUT will be exactly the same as the duty cycle of PWM _IN . The output of interpolator 7A is a digital signal "PWM generator address" on bus 19, which is connected to the channel selector input of output multiplexer 20. Thus, the interpolator 7A generates a selection code on the digital bus 18 to select the desired pattern of PWM signals having the same frequency but slightly different duty cycles, generated by the PWM generator 9A. The output of multiplexer 20 generated on bus 10 is PWM _OUT . Circuitry 15 of FIG. 5 may convert the 8-bit duty cycle information Duty [7: 0] into a filtered or smoothed duty cycle for PWM _OUT .

In FIG. 6, an interpolator circuit 7A is included in an example of the present invention for a particular example, in which the PWM control circuit 1 happens to support only 5 bits of PWM duty cycle resolution. Included in any particular SOC (system-on-chip) integrated circuit. The design of FIG. 6 provides another conventional approach to generating PWM _OUT using a counter to count positive cycle times. FIG. 6 shows a block diagram of a known implementation of the interpolator 7A of FIG. Interpolator 7A includes a 2-bit interpolation multiplexer 28 and an interpolation pattern state machine 29. A 7-bit signal “required PWM duty cycle [6: 0]” is generated on digital bus 6 (FIG. 1) and coupled to two inputs of interpolation pattern state machine 29. Specifically, the most significant MSB bits [6: 2] of the digital word present on the digital bus 6 are the first bits of the interpolation multiplexer 28 as a 5-bit signal “PWM Address Low” on the five bus conductors 27. The same bits of the digital word presented on the input channel on bus 6 are presented to adder 30. The adder 30 adds the additional bit to the PWM Address Low to generate a “one bit higher” address of the input PWM address, and outputs a 5-bit signal “PWM Address High” on another input channel of the interpolation multiplexer 28. Generate More specifically, the least significant 2 LSB bits [1: 0] of the digital word on bus 6 are applied to two inputs of interpolation pattern state machine 29. Interpolation pattern state machine 29 generates a 1-bit input at the channel select input of interpolation multiplexer 28 to provide a predetermined continuous pattern of PWM Address Low or PWM Address High as a 5-bit PWM generator address signal or code on digital bus 19. Is generated.

Interpolator circuit element 7A of FIG. 6 thus receives the 7 MSB bits of the "required PWM duty cycle". A fixed interpolation pattern state machine 29 is used to select or switch between the different multiplexer channel inputs, ie, between "PWM Address Low" and "PWM Address High". This effectively extends the 5-bit duty cycle resolution (2 bits) to a 7-bit PWM duty cycle resolution. PWM generator 9A together with output multiplexer 20 provides a frequency _{f PWM,} a PWM generator address output signal having a duty cycle resolution is limited by the frequency span between the system clock signal frequency _{f sys} and output PWM frequency _{f PWM} . Interpolator 7A and output multiplexer 20 operate to increase duty cycle resolution by interpolating the PWM generator address input. The interpolator circuit element 7A of FIG. 6 selects all of the 32 candidate signals selectable by the PWM duty cycle signal [6: 0] on the bus 6 and uses the interpolation multiplexer 28 to output the PWM generator address. Is generated on the bus 19.

  In a conventional PWM generator without interpolation, only one channel is selected for the MUX input for a given PWM duty cycle. To obtain higher duty cycle resolution, the interpolator 7A of FIG. 5 is designed to provide the function of selecting two adjacent channels in an interleaved pattern. These patterns are designed to achieve the desired higher average duty cycle resolution, ie, duty cycle resolution with smaller duty cycle steps.

FIG. 7 shows a simplified block diagram of the conventional PWM generator 9 of FIG. The PWM generator 9 of FIG. 7 includes an analog ramp generator 33 that receives the PWM _OUT on conductor 10. A digital representation of the output signal _VRAMP generated by the ramp generator 33 in response to PWM _OUT is provided on a 6-bit bus 35, which is provided to an input of a digital comparator 37. The other input of the digital comparator 37 receives a 6-bit duty cycle signal GenDuty [5: 0] on bus 8, which in FIG. 1 is interpolated for the desired duty cycle of the desired PWM output signal PWM _OUT. It is an expression. The digital comparator 37 generates a desired PWM output signal PWM _OUT .

  The PWM duty cycle synthesizer circuit described above may be responsive to a PWM input signal having an input frequency to generate a PWM output signal having an output frequency independent of the input frequency. Typically, the output frequency is higher than the input frequency. The PWM output signal is typically used, for example, to control a motor drive circuit, independent of the user's PWM control signal frequency. The PWM duty cycle synthesizer operates to make the duty cycle of the PWM output signal essentially equal to the duty cycle of the PWM input signal. That is, the duty cycle information defining the duty cycle of the PWM input signal is transferred without any loss of resolution so that the duty cycle of the PWM output signal is equal to the duty cycle of the PWM input signal.

  Thus, the PWM duty cycle synthesizer circuit described above may prevent the controlled motor from suddenly decelerating and / or accelerating in the rotation of the motor. This is due to the sudden transfer of energy between the PWM control electric motor and the power supply due to the duty cycle difference between the PWM input signal and the duty cycle of the PWM output signal generated in response to the PWM input signal. To prevent the occurrence of The PWM duty cycle synthesizer circuit described above can be implemented in a substantially smaller and cheaper integrated circuit with lower design complexity and lower power consumption compared to the state of the art.

  Although the present invention has been described with reference to certain specific embodiments, those skilled in the art will appreciate that various modifications can be made to the described embodiments of the invention without departing from the true spirit and scope of the invention. Would be possible. Elements or elements that perform slightly the same function, respectively, but slightly different from those described in the claims, but in substantially the same way to achieve the same results as those described in the claims. All steps are intended to be included within the scope of the present invention. For example, an analog implementation of delta circuit 3, integrator 5, and PWM generator 9 may be used. It should be noted that the disclosed AND gate may be implemented by any type of logic circuit element that can perform a logical "AND" function.

Claims (14)

A PWM duty cycle synthesizer circuit for generating a PWM output signal having an output frequency in response to a PWM (pulse width modulation) input signal having an input frequency, comprising:
An increment signal is generated if the value of the PWM input signal exceeds a corresponding value of the PWM output signal, and a decrement signal is generated if the value of the PWM input signal is less than the corresponding value of the PWM output signal. A signal comparison circuit to generate;
An integrator circuit for generating a first duty cycle signal representative of a duty cycle of the PWM input signal, wherein the value of the first duty cycle signal is increased in response to each increment signal generated by the signal comparison circuit. An integrator circuit for reducing the value of the first duty cycle signal in response to each decrement signal generated by the signal comparison circuit;
A PWM signal generator circuit for generating the PWM output signal in response to the first duty cycle signal, the plurality of PWM signals having equal duty cycles and different duty cycles to provide an averaged duty cycle. And a interpolator element for selecting a predetermined pattern of the plurality of PWM signals according to a required PWM duty cycle, wherein the PWM output signal substantially corresponds to the duty cycle of the PWM input signal. Said PWM signal generator circuit having equal duty cycles;
A PWM duty cycle synthesizer circuit. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
A PWM duty cycle synthesizer circuit, wherein the output frequency is substantially greater than the input frequency. 3. The PWM duty cycle synthesizer circuit according to claim 2, wherein
A PWM duty cycle synthesizer circuit wherein the output frequency ranges from about 20 kHz (kilohertz) to about 200 kHz and the input frequency ranges from about 2 kHz (kilohertz) to about 100 kHz. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
PWM, wherein the integration circuit is a digital circuit including an up / down counter having a first input coupled to receive the increment signal and a second input coupled to receive the decrement signal. Duty cycle synthesizer circuit. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
A PWM duty cycle synthesizer circuit, wherein the signal comparison circuit does not generate an increment signal or a decrement signal when a duty cycle of the PWM output signal is equal to a duty cycle of the PWM input signal. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
A first inverting circuit having an input coupled to receive the PWM output signal, and a first logical AND circuit having a first input coupled to receive the PWM output signal A second inverting circuit having an input coupled to receive the PWM input signal; and a second logical AND circuit having a first input coupled to receive the PWM input signal. Circuit
A second input of the first logical AND circuit is coupled to an output of the second inverting circuit, and a second input of the second logical AND circuit receives an output of the first inverting circuit. A PWM duty cycle synthesizer circuit, wherein the first and second logical AND circuits are coupled to generate the decrement signal and the increment signal, respectively. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
A ramp generator circuit for generating a ramp signal in response to the PWM output signal; and comparing the ramp signal with the first duty cycle signal to determine whether the PWM output signal is equal to the first duty cycle signal. And a comparator having a duty cycle specified by the duty cycle signal of the PWM duty cycle signal. The PWM duty cycle synthesizer circuit according to claim 7, wherein:
A PWM duty cycle synthesizer circuit, wherein the ramp generator circuit generates a digital representation of the ramp signal, and wherein the comparator is a digital comparator. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
Digital feedback, wherein the signal comparing circuit, the integrating circuit, and the PWM signal generator circuit operate to equalize a duty cycle of the PWM output signal to a duty cycle of the PWM input signal without impairing duty cycle resolution. A PWM duty cycle synthesizer circuit forming a loop. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
A PWM duty cycle synthesizer circuit, wherein the interpolation circuit element generates a second duty cycle signal that is an interpolated representation of the first duty cycle signal. The PWM duty cycle synthesizer circuit according to claim 1 , wherein:
A PWM duty cycle synthesizer circuit, wherein the PWM signal generator circuit further comprises an output multiplexer that selects the predetermined pattern of the plurality of PWM signals based on an output of the interpolator element. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
A PWM duty cycle synthesizer circuit further comprising a motor driver circuit having an input coupled to receive the PWM output signal and an output coupled to drive an electric motor. The PWM duty cycle synthesizer circuit according to claim 1, wherein:
The interpolator generates a selection code in response to the first duty cycle signal;
A PWM duty cycle synthesizer circuit, wherein the PWM signal generator circuit further comprises a selection circuit for selecting the predetermined pattern of the PWM signal in response to the selection code. 14. The PWM duty cycle synthesizer circuit according to claim 13 , wherein:
The interpolation circuit element is:
An address generator for generating an address low signal and an address high signal in response to the first duty cycle signal;
A state machine for generating a channel select signal in response to the first duty cycle signal;
An interpolation multiplexer that generates a PWM generator address as the selection code in response to the address low signal, the address high signal, and the channel selection signal;
A PWM duty cycle synthesizer circuit.