JPH0983379A - Pulse density modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make analog quantity, which is increased with the increase of a pulse density modulation(PDM) code, completely proportional to a PDM code No., by composing a PD modulator of a PDM circuit and a duty adjusting circuit. SOLUTION: This device is provided with a PDM circuit 3, D/A converting circuit 4 and duty adjusting circuit 5. Then, a PD modulator 6 is composed of these PDM circuit 3 and duty adjusting circuit 5. Therefore, the time duration of logic value '1' is widened and the duration of '0' is narrowed and made equal with the value of analog quantity (DC voltage) when '0' before the logic value '1' is changed into '1'. Thus, since the duty adjusting circuit 5 is connected to the PDM circuit 3, the error of DC voltage to be generated can be corrected corresponding to the existence of rising time of pulse of logic value '1' and the increase of DC voltage can be linearly changed corresponding to the increase of PDM code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse density modulator (PDM) device for converting a parallel digital signal related to a base band signal into a serial digital signal, and more particularly to a D / A after pulse density modulation. The present invention relates to a pulse density modulator having improved linearity of analog level (DC voltage) when converted.

[0002]

2. Description of the Related Art In a mobile phone or a car phone using a code division spread (CDMA) system, a digital signal based on a base band signal is controlled by various kinds of analog circuits, for example, AGC.
It is also used for offset voltage control of A / D conversion circuits. This digital signal is weighted to correspond to analog levels of multiple levels. A pulse density modulator generates such a digital signal. For example, a parallel 8-bit (multi-bit) digital signal (256
Input) and obtain a serial (single bit) digital signal at the output. Then, the serial digital signal is converted into 256 analog amounts (that is, DC voltage) by the D / A conversion circuit, whereby AGC is performed.
Are performed.

FIG. 4 shows a conventional structure.
In FIG. 4, 1 is a base band circuit, 2 is a control circuit including a microcomputer, and 3 is a pulse density modulation circuit. The pulse density modulation circuit 3 is disclosed in, for example, US Pat.
Counter and comparator as shown in No. 7,338.
A configuration using a computer is known.

The signal received by the receiving section of the telephone is signal-processed by the base band circuit and then input to the next control circuit 2. The control circuit 2 judges the signal from the base band circuit for bit error, for example, and outputs a parallel 8-bit digital signal for the AGC of the transceiver. This parallel 8-bit digital signal is converted into a serial 256-bit digital signal by the following pulse density modulation circuit for controlling 256 gradations. This serial digital signal is repeatedly generated with 256 bits as one cycle (T). Then, an output weighted in 256 ways is obtained corresponding to the input parallel 8-bit digital signal.

For example, in the first weighted serial digital signal, the first logic value of 256 bits is "1", and the second and subsequent logic values are all "0".
Then, the 257th signal, that is, the first bit of the next cycle, becomes a signal having the logic value "1" again. (This is PDM
Code 1 ) Similarly, every time the PDM code increases by 1, the logic value "1" increases and the PDM code 256
In this case, the logic value of all 256 bits becomes "1". PD
M code NO. The relationship of the position of the logic value "1" with respect to is determined in consideration of ripples and the like when this serial digital signal is converted into analog (DC voltage). Conversion to a DC voltage is performed by the D / A conversion circuit 4.

The ideal relationship between each PDM code of the serial 256-bit digital signal from the pulse density modulation circuit 3 and the DC voltage obtained by converting this into an analog will be described. 5 to 7 are pulse density modulation circuits 3 for PDM code 1, 128 and 256, respectively.
The output signal ((a) in each figure) and the analog-converted DC voltage ((b) in each figure) are shown. FIG. 5 shows the case where the PDM code is 1, the logic value of the first bit is "1", and 256 bits after the second bit is "0". In this case, the DC voltage is E / 256 ( The voltage of logic value "1" is E). Further, FIG. 6 shows the case where the PDM code is 128, the logic value of odd bits is "1" and the logic value of even bits is "0", and in this case, the DC voltage is E / 2. Further, FIG. 7 shows the case where the PDM code is 256, all the logic values of 256 bits are "1", and the DC voltage in this case is E.
Becomes 5 to 7, T represents a time required for 256 bits, and the serial digital signal is repeatedly output with T as a cycle.

[0007]

By the way, as shown in FIG.
The DC voltage shown in FIGS. 6 (b) and 7 (b) operated under ideal conditions in which the rising time and the falling time of the pulse representing the logic value "1" in each PDM code can be ignored. In practice, the rise time and the fall time cannot be ignored due to the influence of the storage capacitance and line inductance in the digital circuit, and in particular, the output impedance when the switching element is turned ON or OFF is Due to the difference, the effect of rise time cannot be ignored. Therefore, when the logic value changes from "0" to "1" due to the change of the PDM code, it becomes "1" depending on whether the next logic value is "0" or "1". The value of the analog-converted DC voltage varies depending on the changed logic value.

For example, in FIG. 8, the logic value is "1", "
In the case of 0 "and" 1 ", it takes time Tr for the pulse to rise completely at the first and third logic values" 1 ". Therefore, depending on this logic value" 1 "( 1
Increase in analog amount (DC voltage)
(A), a portion of the oblique line rising to the right) is smaller than E / 256 when the pulse height is E, and becomes a value of E1 as shown by the dotted line in FIG. This relationship continues until the PDM code is 128. However, when the PDM code exceeds 128, the logic value "0" before the logic value "1" changes to "1", and a part where "1" continues appears. For example, in the case of FIG. 8B in which the logic values change from "1", "0", "1" to "1", "1", "1", the pulse of the third logic value "1" An analog amount that increases each time the PDM code increases by one because the part that was missing at the rising edge is added to the analog amount by the second logic value 0 changing to "1" and continuing. Is E2 which is larger than E / 256 (the portion of the lower right diagonal line in FIG. 8B).

Therefore, the DC voltage at each PDM code is smaller than the value in the ideal state (solid line) up to PDM code 128 as shown by the dotted line in FIG. 10, and the increment (gradient) after PDM code 129. ) Becomes large and becomes a normal value in the PDM code 256. Therefore, when the conventional pulse density modulation circuit is used to perform AGC control, there is a problem in that accurate control cannot be performed.

As a means for solving such a problem, it is conceivable to use a pulse density modulation circuit composed of a high speed logic circuit having an extremely fast pulse rise time, but this is not practical because the device becomes expensive. The object of the present invention is to solve the above-mentioned problems, and by adding a simple circuit, the value of the analog amount increasing with the increase of the PDM code can be completely corrected. To be proportional to.

[0011]

In order to solve the above problems, in the present invention, a pulse density modulation circuit for receiving a multi-bit digital signal and outputting a single-bit digital signal, and a duty of the single-bit digital signal. A pulse density modulator was constructed from a duty adjustment circuit that outputs with a changed cycle.

Further, in the present invention, the duty adjusting circuit comprises a delay circuit and a logical sum circuit, and the delay circuit delays the single bit digital signal for a predetermined time and supplies it to one input terminal of the logical sum circuit. The single bit digital signal is supplied to the other input terminal of the OR circuit. Further, in the present invention, the delay circuit is composed of a resistor and a capacitor, and the resistor is a variable resistor. Further, in the present invention, a filter means for filtering the single bit digital signal from the duty adjustment circuit is provided, and this filter means is a D / A conversion circuit or a low pass filter.

[0013]

According to the above means, the time width of the logic value "1" becomes wider and the width of "0" becomes narrower, so that the analog value (DC voltage) value and the logic value "1" depending on the logic value "1" become Analog quantity (DC voltage) when the previous "0" changed to "1"
Is equal to the value of.

[0014]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a pulse density modulator according to the present invention, and FIG.
Shows a concrete circuit of the characteristic part. In FIG. 1, 3 and 4 are the same pulse density modulation circuit and D / A conversion circuit as the conventional one,
A duty adjusting circuit 5 is a feature of the present invention. The pulse density modulator 3 and the duty adjustment circuit 5 constitute a pulse density modulator. 2 is a specific circuit of the duty adjusting circuit 5 in FIG. 1, and 7 is an OR circuit (OR circuit),
Reference numeral 8 denotes an integrating circuit including a variable resistor 9 and a capacitor 10. Instead of the D / A conversion circuit 4, a low pass filter or an integration circuit can be used.

The output from the pulse density modulation circuit 3 is input to one input terminal of the logical sum circuit 7 and is also input to the other logical sum circuit via the variable resistor 9 in series. The capacitor 10 is connected between the other input terminal of the OR circuit 7 and the ground. The operation when the serial data from the PDM modulation circuit 3 is input to the duty adjustment circuit 5 thus connected will be described below.

FIG. 3 shows the input waveform of the serial data in the duty adjusting circuit 5. In FIG. 3, (a) shows a waveform input from the pulse density modulation circuit 3 to one input terminal of the logical sum circuit of the duty adjustment circuit 5, and as an example, logic values “1”, “0”, “1”. 3 bits are shown. The duty of each of the logic values "1", "0", and "1" is the same Td. This serial data is input to the other input terminal of the logical sum circuit 7 via the integrating circuit 8. This waveform is delayed by the time Δt from the waveform shown in (a) by the integrating circuit 8 as shown in (b) and is input to the other input terminal of the logical sum circuit 7. From the OR circuit 7 to which the waveforms of (a) and (b) above are input, as shown in (c) of the figure, the time of the logic value "1" is T1 longer than Td, and the logic value "0".
Becomes T2, which is shorter than Td, and is output as a signal with a changed duty ratio.

In this case, T1 + T2 = 2Td, but T1, T
The time of 2 can be adjusted by changing the time constant of the integrating circuit 8. In this embodiment, the time constant can be changed by changing the value of the resistor 9. Then, by appropriately setting T1 and T2, the area indicated by the diagonal line rising to the right at the first logic value "1" and the diagonal line descending to the right when the second logic value "0" changes to 1 The areas indicated by can be made equal. By using the duty adjusting circuit adjusted in this way, the analog amount increment by the logic value "1" can be made equal to E / 256 until the PDM code is 128, and the PDM code is from 129. Two
The increment of the analog amount by one pulse when the logic value "0" changes to 1 up to 56 can also be made equal to E / 256. This is shown by the solid lines in FIGS. 9 and 10. It can be seen from FIG. 10 that the DC voltage converted into the analog amount changes linearly with the increase of the PDM code.

[0018]

As described above, in the pulse density modulator of the present invention, by connecting the duty adjusting circuit to the pulse density modulating circuit, the error of the DC voltage generated by the existence of the rise time of the "pulse" having the logic value of 1 "is obtained. Since the PDM code can be corrected, the increase in the DC voltage with respect to the increase in the PDM code can be changed linearly. Therefore, it is possible to accurately control the AGC and the like. Further, according to the present invention, it is not necessary to use a high speed and expensive logic circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a pulse density modulator according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a main part of a pulse density modulator according to the present invention.

FIG. 3 is an operation explanatory diagram of a main part of the pulse density modulator according to the present invention.

FIG. 4 is a partial block diagram of a receiver including a conventional pulse density modulator.

FIG. 5 is an explanatory diagram of an ideal operation of the pulse density modulator.

FIG. 6 is an explanatory diagram of an ideal operation of the pulse density modulator.

FIG. 7 is an explanatory diagram of an ideal operation of the pulse density modulator.

FIG. 8 is an operation explanatory diagram of a conventional pulse density modulator.

FIG. 9 is an explanatory diagram of a relationship between a PDM code and a DC voltage in a pulse density modulator.

FIG. 10 is an explanatory diagram of a relationship between a PDM code and a DC voltage in a pulse density modulator.

[Explanation of symbols]

 1 Baseband Circuit 2 Control Circuit 3 Pulse Density Modulation Circuit 4 D / A Converter Circuit 5 Duty Adjustment Circuit 6 Pulse Density Modulator 7 OR Circuit 8 Integration Circuit 9 Variable Resistor 10 Capacitor

Claims (7)

[Claims] 1. A pulse density modulating means for receiving a multi-bit digital signal and outputting a single-bit digital signal, and a duty adjusting means for changing and outputting a pulse width of the single-bit digital signal. Pulse density modulator. 2. The duty adjusting means comprises a delay circuit and a logical sum circuit, the delay circuit delays the single bit digital signal for a predetermined time and supplies the delayed single bit digital signal to one input terminal of the logical sum circuit. 2. The pulse density modulator according to claim 1, wherein the single bit digital signal is supplied to the other input terminal of the OR circuit. 3. The pulse density modulator according to claim 2, wherein the delay circuit is an integrating circuit including a resistor and a capacitor. 4. The pulse density modulation circuit according to claim 3, wherein the resistor is a variable resistor. 5. The pulse density modulator according to claim 1, wherein the pulse density modulator includes filter means for filtering a single bit digital signal from the duty adjusting means. . 6. The pulse density modulator according to claim 5, wherein the filter means is a D / A conversion circuit. 7. The pulse density modulator according to claim 5, wherein the filter means is a low-pass filter.