JPS5965552U - semiconductor thyristor device - Google Patents
semiconductor thyristor deviceInfo
- Publication number
- JPS5965552U JPS5965552U JP1982160087U JP16008782U JPS5965552U JP S5965552 U JPS5965552 U JP S5965552U JP 1982160087 U JP1982160087 U JP 1982160087U JP 16008782 U JP16008782 U JP 16008782U JP S5965552 U JPS5965552 U JP S5965552U
- Authority
- JP
- Japan
- Prior art keywords
- brazed
- thyristor device
- semiconductor
- semiconductor thyristor
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は、従来のサイリスタペレット、第2図は、従来
のサイリスタ組立図、第3図a、 bは、本考案実施
例のカソード連結線、第4図はその組立図である。
なお、図中の符号は、1・・・・・・Nベース、2・・
曲Pベース、3・・・・・・Pエミッタ、4・・・・・
・Nエミッタ、5・・・・・・Pベース露出部、6・・
・・・・カソード電極、7・・・・・・アノード電極、
8・・・・・・ゲート電極、11・・・・・・スタッド
、12・・・・・・下部補強板、13・・・・・・ペレ
ット、14・・・・・・上部補強板、15.15’・・
・・・・カソード連結線、16.16’・・・・・・ゲ
ートリード線、7・・・・・・ろう材、である。FIG. 1 is a conventional thyristor pellet, FIG. 2 is an assembly diagram of a conventional thyristor, FIGS. 3a and 3b are cathode connection lines of an embodiment of the present invention, and FIG. 4 is an assembly diagram thereof. Note that the symbols in the figure are 1...N base, 2...
Song P base, 3...P emitter, 4...
・N emitter, 5...P base exposed part, 6...
... Cathode electrode, 7 ... Anode electrode,
8... Gate electrode, 11... Stud, 12... Lower reinforcing plate, 13... Pellet, 14... Upper reinforcing plate, 15.15'...
. . . Cathode connection wire, 16.16' . . . Gate lead wire, 7 . . . Brazing material.
Claims (1)
タッドにろう付けされ、第2の主表面のキード部にゲー
トリード線、カソード部に熱補償板を介してカソード連
結線がそれぞれろう付けされている半導体サイリスタ装
置において、前記カソード連結線に、前記ゲートリード
線の幅より広いスリットを設けたことを特徴とする半導
体サイリスク装置。The first main surface of the semiconductor pellet is brazed to the stud via a heat compensator, the gate lead wire is brazed to the keyed part of the second main surface, and the cathode connecting wire is brazed to the cathode part via the heat compensator. A semiconductor thyristor device, characterized in that the cathode connecting line is provided with a slit wider than the width of the gate lead line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982160087U JPS5965552U (en) | 1982-10-22 | 1982-10-22 | semiconductor thyristor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982160087U JPS5965552U (en) | 1982-10-22 | 1982-10-22 | semiconductor thyristor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5965552U true JPS5965552U (en) | 1984-05-01 |
Family
ID=30352211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982160087U Pending JPS5965552U (en) | 1982-10-22 | 1982-10-22 | semiconductor thyristor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5965552U (en) |
-
1982
- 1982-10-22 JP JP1982160087U patent/JPS5965552U/en active Pending
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