JPS5965551U - Thick film hybrid integrated circuit - Google Patents

Thick film hybrid integrated circuit

Info

Publication number
JPS5965551U
JPS5965551U JP16195082U JP16195082U JPS5965551U JP S5965551 U JPS5965551 U JP S5965551U JP 16195082 U JP16195082 U JP 16195082U JP 16195082 U JP16195082 U JP 16195082U JP S5965551 U JPS5965551 U JP S5965551U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
thick film
lead frame
film hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16195082U
Other languages
Japanese (ja)
Inventor
昌己 木下
彰 山川
Original Assignee
日本無線株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本無線株式会社 filed Critical 日本無線株式会社
Priority to JP16195082U priority Critical patent/JPS5965551U/en
Publication of JPS5965551U publication Critical patent/JPS5965551U/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の厚膜混成集積回路を示す斜視図、第２図
は本考案の実施例を示す斜視図、および第３図は重複領
域と接合強度との関係を示すグラフである。 １：・・混成集積回路基板、２・・・厚膜焼成金属パタ
ーン、２′・・・機能素子取付ランド、−２″・・・リ
ードフレーム取付ランド、３・・・誘電体、３′・・・
重複領域、４・・・機能素子、５・・・半田材料。FIG. 1 is a perspective view showing a conventional thick film hybrid integrated circuit, FIG. 2 is a perspective view showing an embodiment of the present invention, and FIG. 3 is a graph showing the relationship between overlapping area and bonding strength. 1: Hybrid integrated circuit board, 2... Thick film fired metal pattern, 2'... Functional element mounting land, -2''... Lead frame mounting land, 3... Dielectric, 3'.・・・
Overlapping region, 4... functional element, 5... solder material.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）混成集積回路基板上に設けられた、厚膜焼成金属
パターンにおけるリードフレームを取付けるためのリー
ドフレーム取付ランドの周辺端部を誘電体で被覆して重
複した領域を形成することによって、前記リードフレー
ムの前記混成集積回路基板への接合強度を増大せしめた
ことを特徴とする厚膜混成集積回路。(1) Covering the peripheral edge of a lead frame mounting land for attaching a lead frame in a thick film fired metal pattern provided on a hybrid integrated circuit board with a dielectric material to form an overlapping area; A thick film hybrid integrated circuit characterized in that the bonding strength of the lead frame to the hybrid integrated circuit board is increased. （２）実用新案登録請求の範囲第１項の回路において、
前記重複領域における、前記周辺端部から該周辺に垂直
な方向における距離が、前記り−ドフレーム取付ランド
の膜厚の約８倍以上であることを特徴とする厚膜混成集
積回路。(2) In the circuit set forth in paragraph 1 of the claims for utility model registration,
A thick film hybrid integrated circuit characterized in that a distance in the overlapping region from the peripheral edge in a direction perpendicular to the peripheral is about 8 times or more the thickness of the read frame mounting land.
JP16195082U 1982-10-26 1982-10-26 Thick film hybrid integrated circuit Pending JPS5965551U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16195082U JPS5965551U (en) 1982-10-26 1982-10-26 Thick film hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16195082U JPS5965551U (en) 1982-10-26 1982-10-26 Thick film hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5965551U true JPS5965551U (en) 1984-05-01

Family

ID=30355766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16195082U Pending JPS5965551U (en) 1982-10-26 1982-10-26 Thick film hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5965551U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0364052A (en) * 1989-08-02 1991-03-19 Hitachi Ltd Hybrid integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0364052A (en) * 1989-08-02 1991-03-19 Hitachi Ltd Hybrid integrated circuit

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