JPS5961954A - Semiconductor resistance element - Google Patents

Semiconductor resistance element

Info

Publication number
JPS5961954A
JPS5961954A JP17088582A JP17088582A JPS5961954A JP S5961954 A JPS5961954 A JP S5961954A JP 17088582 A JP17088582 A JP 17088582A JP 17088582 A JP17088582 A JP 17088582A JP S5961954 A JPS5961954 A JP S5961954A
Authority
JP
Japan
Prior art keywords
layer
type
diffusion
resistance
potential side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17088582A
Other languages
Japanese (ja)
Inventor
Makoto Ishikawa
誠 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17088582A priority Critical patent/JPS5961954A/en
Publication of JPS5961954A publication Critical patent/JPS5961954A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802Resistors only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605Resistors with PN junctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a pinch resistor as to enable to control a current to flow at breakdown time by a method wherein a second diffusion resistance layer the same conductive type with a first diffusion resistance layer is continuously connected to the low electric potential side of the first diffusion resistance layer as the diffusion layer united in one body of both. CONSTITUTION:A first p type base diffusion resistance layer 4 is formed on the surface of an island region 2 consisting of an n type epitaxial layer, an n<+> type emitter diffusion layer 5 is provided at a part of the surface thereof to convert the p type diffusion layer 7 positioning directly thereunder into high resistance, the second p type diffusion resistance layer 8 is continuously connected being united in one body to the low electric potential side (the L side) of the p type diffusion layers 4, 7, and electrodes H, L to be connected respectively ohmically to the high electric potential side (the H side) and the low electric potential side are provided. The resistance value of the first p type diffusion layer 4 converted into high resistance is designated as R1, the resistance value of the second p type diffusion layer 8 continuously connected to the low electric potential side is designated as R2, and when a breakdown voltage is applied between the electrodes H and L, because resistance is divided into R1 and R2, a reverse bias voltage applied to p-n junction of the n<+> type layer 5 and the p type layer 4 is restrained under the breakdown voltage. Moreover, even when breakdown is generated, because the R2 component survives, the current can be controlled.

Description

【発明の詳細な説明】 本発明は半導体拡散層による・高抵抗素子に関する。[Detailed description of the invention] The present invention relates to a high resistance element using a semiconductor diffusion layer.

半導体集権回路装置においては回路の一部として半導体
基体の島領域内にトランジスタのベース拡散層を利用し
た抵抗素子が知られている。この拡散抵抗はベース拡散
濃度が比較的に高く、又半導体の島領域は面積が限られ
ていることにより。
2. Description of the Related Art In semiconductor integrated circuit devices, a resistance element is known that utilizes a base diffusion layer of a transistor within an island region of a semiconductor substrate as a part of the circuit. This diffusion resistance is due to the fact that the base diffusion concentration is relatively high and the area of the semiconductor island region is limited.

このままでは高抵抗が得られないためエミ・ンタ拡散を
利用したピンチ抵抗が考えられでいろ。このピンチ抵抗
は第1図、第2図に示すようにp型S1(シリコン)基
板1上にエピタキシャル成長させたn型Si7%5をp
型拡散アイソレーショ/層3により島領域として他から
隔離したn型領域の一つにnpn)ランジスタのベース
拡散を利用して特定のパターンをもつp型拡赦抵抗層4
を形成し。
Since high resistance cannot be obtained as is, a pinch resistance using emitter diffusion may be considered. As shown in FIGS. 1 and 2, this pinch resistance consists of a p-type Si 7%5 layer epitaxially grown on a p-type S1 (silicon) substrate 1.
In one of the n-type regions isolated from the others as an island region by type diffusion isolation/layer 3, a p-type ambiguous resistor layer 4 having a specific pattern using base diffusion of a transistor is formed.
form.

次いでエミッタ拡散を利用してp型拡散抵抗層40表面
の一部を横切るようにn+型型数散層5形成したもので
ある。同図の6は酸化シリコン(siot)等からなる
絶縁膜、H,Lは拡散抵抗の両端にオーミックコンタク
トするi(アルミニウム)電極であろうこのようにp型
拡赦抵抗4はその一部°に形成されたn+型型数散層5
よって抵抗面積が狭くなりn十型拡散層直下の部分(ピ
ッチ部)7に高抵抗部貼をもっことになる。このような
拡散抵抗においてはn+型拡赦層5のp型拡散層4から
はみ出した部分がエピタキシャルn型層2に爪な−でい
るために2n+型拡散層5とn型層2とは四m位にある
Next, an n+ type scattering layer 5 is formed across a part of the surface of the p type diffused resistance layer 40 using emitter diffusion. In the figure, 6 is an insulating film made of silicon oxide (SIOT), etc., and H and L are i (aluminum) electrodes that make ohmic contact with both ends of the diffused resistor.As shown, the p-type amended resistor 4 is a part of it. n+ type scattered layer 5 formed in
Therefore, the resistance area becomes narrower, and a high resistance part is attached to the part (pitch part) 7 directly under the n-type diffusion layer. In such a diffused resistance, the portion of the n+ type diffusion layer 5 protruding from the p type diffusion layer 4 is in contact with the epitaxial n type layer 2, so that the 2n+ type diffusion layer 5 and the n type layer 2 are It is at position m.

ところで同図において電極[1側を高m位、T江極り側
を低電位として、抵抗のγ比位差が高くなり。
By the way, in the same figure, when the electrode [1 side is set to a high potential and the T end side is set to a low potential, the γ ratio potential difference of the resistance increases.

耐電圧(例えば7V)以上になった場合、低電位側のp
型層内の空乏層8でブレークダウン(降伏)を起し、H
,L間に電流が無制限f流れろことb・ら回路が破壊す
るおそれがあることがわか〜た。
When the withstand voltage (e.g. 7V) or higher, the low potential side p
Breakdown occurs in the depletion layer 8 in the type layer, and H
It has been found that there is a risk that an unlimited current flows between f, L and b, and the circuit may be destroyed.

本発明は上記した欠点を取り除(ためになされたもので
あり、その目的とするところは、ブレークダウ7時の電
流を制御できる改良されたピンチ抵抗を提供することに
ある。
The present invention has been made to eliminate the above-mentioned drawbacks, and its object is to provide an improved pinch resistor that can control the current during breakdown.

本発明の一実施例として第3図、第4図にICの一部と
して形成された半導体抵抗素子が示される。この半導体
抵抗素子は、工゛Yタキシャルn型層からなる島領域2
0表面に第1のp型ベース拡散抵抗FVJ4を形成(−
1このp型拡散の表面の一部にn++エミッタ拡散層5
を設けてその直下のp型拡散層7を託抵抗化した半導体
抵抗素子において、高抵抗化されたp型拡散層4.7の
低電位側(LIBj)に第2のp型拡散抵抗層8を一体
的に連設し、高電位側(H側)と低電位側にそれぞれオ
ーミック接続する市% H、Lを設けたものである。
As one embodiment of the present invention, FIGS. 3 and 4 show a semiconductor resistance element formed as a part of an IC. This semiconductor resistance element has an island region 2 made of a Y taxial n-type layer.
A first p-type base diffused resistor FVJ4 is formed on the surface of 0 (−
1 An n++ emitter diffusion layer 5 is formed on a part of the surface of this p-type diffusion.
In the semiconductor resistance element in which the p-type diffusion layer 7 directly under the p-type diffusion layer 7 is made to have high resistance, a second p-type diffusion resistance layer 8 is provided on the low potential side (LIBj) of the high-resistance p-type diffusion layer 4.7. are integrally connected, and ohmic connections H and L are provided on the high potential side (H side) and the low potential side, respectively.

このような半導体抵抗の構造においては、高抵抗化され
た部分(7)を含む第1のp型拡散層4の抵抗値を1モ
7.低電位側に連設された第2のp型拡赦層8の抵抗値
をIモ、として1電極H−L間にブレークダウ/m圧(
例えば7v)がθ)かった場合に、抵抗は)も、とR2
に分割されているため、+型層5とp型J’f!j 4
とのpn接合にかかる逆バイアス電圧はブレークダウン
亀圧以Fに(例えば3〜4V)におさえられろことによ
りブレークダウンが生じないったとえブレークダウンし
でもR2成分が残るために電流を制御することができる
In such a semiconductor resistor structure, the resistance value of the first p-type diffusion layer 4 including the high resistance portion (7) is set to 1.7. Assuming that the resistance value of the second p-type amended layer 8 connected to the low potential side is Imo, the breakdown/m pressure (
For example, if 7v) is θ), the resistance is also R2
Since it is divided into + type layer 5 and p type J'f! j 4
The reverse bias voltage applied to the pn junction should be kept below the breakdown voltage (for example, 3 to 4 V) so that breakdown does not occur. Even if breakdown occurs, the R2 component remains, so the current is controlled. be able to.

以上、実施例で述べたように本発明によればn+型型数
散層より高抵抗化したp型拡散抵抗の低電位側に一つの
抵抗分を付加することでブレークダウン時にも電流の制
御ができ、ピンチ抵抗の範囲を広げることができ2従っ
て限られた半導体チップ面積で高抵抗が得られるという
前記の目的を達成できる。
As described above in the embodiments, according to the present invention, the current can be controlled even during breakdown by adding one resistance to the low potential side of the p-type diffused resistor, which has a higher resistance than the n+ type diffused layer. This makes it possible to widen the range of pinch resistance.2 Therefore, the above-mentioned objective of obtaining high resistance with a limited semiconductor chip area can be achieved.

本発明は前記実施例に限定されない。すなわち抵抗のパ
ターンはこれ以外にも種々の形態を利用する′ことがで
きる。
The invention is not limited to the above embodiments. In other words, the resistor pattern can have various forms other than this.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこれまでの半導体抵抗素子の一例を示す平面図
。 第2図は第1図におけるA−N切断断面図であるう 第3図は本発明による半導体抵抗素子の一実癲例を示す
平面図。 第4図は第3図におけるB −8’切切断面図である。 l・・・pilJJ、Si i板、2・・・エピタキシ
ャルn型層。 3・・・アイソレーションp型層、4・・・(第1))
p型拡散抵抗層、5・・・n+型拡赦層、6・・・絶縁
膜。 7・・・ビ/テ抵抗部、8・・・第2のp型拡散抵抗層
。 代理人 弁理士  薄 1)利 幸 少 第  1  図 第  2 図 第  4  図
FIG. 1 is a plan view showing an example of a conventional semiconductor resistance element. FIG. 2 is a sectional view taken along the line AN in FIG. 1. FIG. 3 is a plan view showing an example of a semiconductor resistance element according to the present invention. FIG. 4 is a sectional view taken along line B-8' in FIG. 3. l... pilJJ, Si i plate, 2... epitaxial n-type layer. 3... Isolation p-type layer, 4... (1st))
p-type diffused resistance layer, 5...n+ type tolerance layer, 6... insulating film. 7...V/T resistance section, 8...Second p-type diffused resistance layer. Agent Patent Attorney Usui 1) Yukisho Tori Figure 1 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】 1、半導体基体表面に形成した第1の拡散抵抗層の表面
の一部にこの拡散抵抗層と導電型の異なる高濃度拡散層
を設けてなる半導体抵抗素子において、この第1の拡散
抵抗層の低電位側にこの第1の拡散抵抗層と同じ導電型
の第2の拡散抵抗層を連設したことを特徴とする半導体
抵抗素子。 2− 第1の拡散抵抗層と第2の拡散抵抗層は一体の拡
散層として形成されている特[yl請求の範囲第1項に
記載の半導体抵抗素子。 3、第1及び第2の拡散抵抗層は同じ半導体基体表面に
形成されたトランジスタのベース拡散層な利用し、導電
型の異なる高濃度拡散層は同じ(エミッタ拡散層を利用
したものである特許請求の範囲第1項又は第2項に記載
の半導体抵抗素子。
[Claims] 1. A semiconductor resistance element in which a high concentration diffusion layer having a conductivity type different from that of the first diffusion resistance layer is provided on a part of the surface of the first diffusion resistance layer formed on the surface of the semiconductor substrate. A semiconductor resistance element characterized in that a second diffused resistance layer of the same conductivity type as the first diffused resistance layer is successively provided on the low potential side of the first diffused resistance layer. 2- The semiconductor resistance element according to claim 1, wherein the first diffusion resistance layer and the second diffusion resistance layer are formed as an integrated diffusion layer. 3. The first and second diffusion resistance layers are used as base diffusion layers of transistors formed on the surface of the same semiconductor substrate, and the high concentration diffusion layers of different conductivity types are the same (patent that uses an emitter diffusion layer). A semiconductor resistance element according to claim 1 or 2.
JP17088582A 1982-10-01 1982-10-01 Semiconductor resistance element Pending JPS5961954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17088582A JPS5961954A (en) 1982-10-01 1982-10-01 Semiconductor resistance element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17088582A JPS5961954A (en) 1982-10-01 1982-10-01 Semiconductor resistance element

Publications (1)

Publication Number Publication Date
JPS5961954A true JPS5961954A (en) 1984-04-09

Family

ID=15913114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17088582A Pending JPS5961954A (en) 1982-10-01 1982-10-01 Semiconductor resistance element

Country Status (1)

Country Link
JP (1) JPS5961954A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62163359A (en) * 1986-01-14 1987-07-20 Sanyo Electric Co Ltd Semiconductor resistance device
JP2008021962A (en) * 2006-06-12 2008-01-31 Ricoh Co Ltd Resistive element adjusting method, resistive element adjusted for resistance value and temperature dependency by method, and current generating device using resistive element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62163359A (en) * 1986-01-14 1987-07-20 Sanyo Electric Co Ltd Semiconductor resistance device
JP2008021962A (en) * 2006-06-12 2008-01-31 Ricoh Co Ltd Resistive element adjusting method, resistive element adjusted for resistance value and temperature dependency by method, and current generating device using resistive element

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