JP2008021962A - Resistive element adjusting method, resistive element adjusted for resistance value and temperature dependency by method, and current generating device using resistive element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust a resistance value and a temperature dependency of a resistive element consisting of a well resistor formed on a semiconductor substrate. <P>SOLUTION: Contact regions 6 are formed to be away from each other, at two points in a well resistance region 4. A contact 10 is formed on the contact region 6 through a silicide layer 8. Between the contact regions 6 in the well resistance region 4, a P<SP>+</SP>diffusion region 14 is formed to adjust a resistive value and a temperature dependency of the resistive element. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for adjusting a resistance value and a temperature dependency characteristic of a resistance element formed of a well resistance region formed on a semiconductor substrate, a resistance element having an adjusted resistance value and a temperature dependency characteristic, and current generation using the resistance element It relates to the device.

In recent years, in order to improve the digital operation speed, the miniaturization of the gate electrode in the semiconductor device has progressed. On the other hand, the semiconductor device is also used for analog applications as represented by power supply products.
In analog circuits, variations in resistance and capacitance of semiconductor devices, as well as temperature-dependent characteristics and voltage-dependent characteristics greatly affect circuit characteristics. In particular, variation in characteristics due to temperature change is not negligible in an analog circuit even if it is negligible in a digital circuit.

  Therefore, the temperature dependence characteristics of the semiconductor device must be leveled over the entire temperature range. As the method, for example, there is a method of configuring a circuit so as to cancel each other's temperature-dependent characteristics using two elements having different temperature-dependent characteristics. A circuit having such a configuration will be described with reference to FIG.

FIG. 12 shows a constant current circuit. In this figure, 44 is an operational amplifier (hereinafter referred to as an operational amplifier), M1, M2 and M3 are the same pair MOS transistors, Q1 and Q2 are bipolar transistors, and R is a resistance element.
Transistors M1, M2, and M3 are connected to the same power supply terminal 38 at their respective sources to form a current mirror connection. The bipolar transistors Q1 and Q2 have the same characteristics, and the base-emitter area ratio is 1: n (n> 1).

Since negative feedback is applied so that the input voltage of the inverting input terminal (− terminal) of the operational amplifier 44 is equal to the input voltage of the non-inverting input terminal (+ terminal), both ends of the resistor R have bipolar transistor Q1. A difference ΔV _BE between the base-emitter voltage V _BE1 and the base-emitter voltage V _BE2 of the bipolar transistor Q2 is applied. Since the transistors M1, M2, and M3 are in a current mirror connection, their drain currents are equal to the reference current I. Saturation current I _S2 of the bipolar transistor Q2 is n times the saturation current I _S1 of the bipolar transistor Q1, the transistor M1 and M2 are connected in a current mirror, the bipolar transistors Q1 and Q2 each emitter currents equals current I ₀ And can be expressed by the following equation (1).

ΔV _BE = V _BE1 −V _BE2
= Vt × ln (I ₀ / I _S1 ) −Vt × ln (I ₀ / I _S2 )
= Vt × ln (n) (1)
However, Vt represents a thermal voltage, and Vt = kT / q. k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge.
Here, k = 1.38 × 10 ⁻¹³ (J / K) and q = 1.6 × 10 ⁻¹⁹ (C).

Since ΔV _BE = I × R and I = Vt × ln (n) / R, the temperature dependence coefficient TC (I) of the reference current I is expressed by the following equation (2).
TC (I) = 1 / I x ∂I / ∂T
= TC (Vt) + TC (1 / R)
= TC (Vt) -TC (R) (2)
Therefore, from the above equation (2), TC (Vt) is 3333 ppm / ° C. when the reference temperature is an absolute temperature of 300K. That is, by setting the temperature dependency coefficient TC (R) of the resistor R to 3333 ppm / ° C., the temperature dependency coefficient TC (I) of the reference current becomes zero.

Here, the temperature dependence coefficient TC (R) of the resistor R can be obtained by the following equation (3).
TC (R) = (R _T −R _RT ) / R _RT (3)
R _T is a resistance value at a reference temperature, and R _RT is a resistance value at room temperature (for example, 25 ° C.).

  As the resistance R of the constant current circuit as shown in FIG. 12, for example, a resistance element having a well resistance as shown in FIG. 16 is used. FIG. 16 is a view showing an example of a resistance element made of a well resistance element, (A) is a plan view showing the structure of the resistance element formed on the semiconductor substrate, and (B) is an FF of (A). It is sectional drawing in a position.

In the resistance element shown in FIG. 16, an N well resistance region 4 is formed on the main surface side of the semiconductor substrate 2, and a contact region 6 composed of a high concentration N ⁺ diffusion region is formed in the vicinity of both ends thereof. . An element isolation film 46 made of, for example, a silicon oxide film having an STI (Shallow Trench Isolation) structure is formed at both ends of the N well resistance region 4 to be electrically isolated. In addition, an element isolation film 46 is formed in a portion other than the contact region 6 of the N well resistance region 4. A silicide layer 8 and a contact 10 are formed on the contact region 6.
JP 2000-31269 A

In the resistance element shown in FIG. 16, it is proposed that the resistance value of the well resistance region 4 is lowered by devising the method of forming the element isolation film 46 and forming the N well deeply in order to effectively suppress the substrate bias. (For example, see Patent Document 1).
However, this method can adjust the resistance value of the well resistance region 4, but cannot adjust the temperature-dependent characteristic of the resistance value. For this reason, a method for adjusting the temperature characteristics of the entire resistance element by combining a well resistance and another resistance element having a different temperature-dependent characteristic has been proposed. It was difficult to obtain temperature dependent characteristics.

  Accordingly, an object of the present invention is to make it possible to adjust the resistance value and temperature dependent characteristics of a resistance element formed of a well resistance formed on a semiconductor substrate.

The resistance element adjustment method of the present invention adjusts the resistance value and temperature dependence characteristics of a resistance element including a well resistance region formed in a semiconductor substrate and contact regions formed in the well resistance region so as to be separated from each other. And a diffusion region for adjusting a resistance value and a temperature-dependent characteristic is formed on the surface side between the contact regions in the well resistance region.
The resistance element of the present invention has a resistance value and a temperature dependency characteristic adjusted by the resistance element adjustment method of the present invention. The resistance value and the temperature dependency characteristic are provided on the surface side between the contact regions in the well resistance region. A diffusion region for adjustment is formed.

In the resistance element adjusting method and the resistance element of the present invention, the diffusion region formed in the well resistance region may have a conductivity type opposite to the well resistance region, or may be the same conductivity type as the well resistance region. .
If the diffusion region has a conductivity type opposite to the well resistance region, the resistance value of the well resistance region decreases. If the diffusion region has the same conductivity type, the resistance value of the well resistance region further decreases.

  A silicide layer may be formed on the surface side of the diffusion region formed in the well resistance region. Then, the resistance value of the well resistance region can be adjusted to be lower.

  The present inventors have formed a diffusion region different from the well resistance region between two contact regions provided in the vicinity of both ends of the well resistance region. It was found that can be changed. Furthermore, it has been found that the temperature dependent characteristic, that is, the temperature dependent coefficient can be adjusted by changing the ratio of the area occupied by the diffusion region for adjusting the temperature dependent characteristic in the well resistance region. Data indicating this is shown in FIG.

FIG. 17 is a graph showing the relationship between the area ratio (%) occupied by the P ⁺ diffusion region in the N-type well resistance region and the temperature dependency coefficient (ppm / ° C.) of the resistance element.
From this graph, it can be seen that the temperature dependence coefficient depends on the area ratio of the P ⁺ diffusion region in the well resistance region. As shown in FIG. 16, the temperature dependence coefficient when the P ⁺ diffusion region is not formed in the well resistance region (area ratio is 0%) is about 3350 ppm / ° C. If the P ⁺ diffusion region is formed in the resistance region at an area ratio of 50%, the temperature dependence coefficient is increased to 3600 ppm / ° C. From this result, the temperature dependence coefficient can be increased by increasing the area ratio occupied by the P ⁺ diffusion region in the N-type well resistance region, and conversely, if the area ratio occupied by the P ⁺ diffusion region is decreased, the temperature dependence coefficient is increased. It was found that can be reduced.

  Therefore, in the resistance element adjusting method and the resistance value of the present invention, it is preferable to adjust the resistance value and the temperature-dependent characteristic of the resistance element by changing the area ratio of the diffusion region in the well resistance region.

Before forming the diffusion region for adjusting the resistance value and the temperature-dependent characteristics, it is preferable to form an element isolation film around the region where the diffusion region in the well resistance region is to be formed.
In particular, the element isolation film is formed by etching a semiconductor substrate in a region where the element isolation film is formed to form a depression, and an insulating film is formed on the semiconductor substrate including the depression by deposition, and then the insulating film is formed only on the depression by planarization. You may make it form by leaving. That is, the element isolation film may have an STI structure embedded in a semiconductor substrate. By forming the element isolation film in the STI structure, the surface of the semiconductor substrate is flattened. Therefore, even if ion implantation of impurities is performed on a region where the element isolation film is formed and a region where the element isolation film is not formed. Impurities can be implanted at a position at a uniform depth from the surface of the semiconductor substrate. Therefore, when the element isolation film is formed with the STI structure, the impurity implantation for forming the well resistance region can be performed after the element isolation film is formed.
Furthermore, if the formation region of the diffusion region is defined by the element isolation film having the STI structure, the diffusion region can be formed in a self-aligned manner, and the impurity implanted into the formation region is more than the formation region. Diffusion outside can be prevented by the element isolation film.

  The impurity implantation for forming the diffusion region preferably uses a process for forming an element in another region of the semiconductor substrate.

  The element isolation film may be an insulating film embedded in a depression formed in a semiconductor substrate, that is, an STI structure, or a LOCOS (local oxidation of silicon) oxide film. May be.

  The resistance element of the present invention can also be applied to an element having a plurality of well resistance regions. For example, diffusion for adjusting resistance value and temperature-dependent characteristics in at least one well resistance region. The thing in which the area | region was formed can be mentioned.

  The current generator of the present invention includes a voltage generator that generates a voltage having an inherent dependence on a temperature change, a resistance element to which a voltage generated by the voltage generator is applied at both ends, a voltage and a resistance element And a current output unit that outputs a current according to each of the temperature characteristics, and the resistance element for temperature characteristic adjustment of the present invention is used as the resistance element.

In the resistance element adjusting method of the present invention, the diffusion region for adjusting the resistance value and the temperature dependence characteristic is formed on the surface side between the contact regions in the well resistance region. A resistance element having dependency characteristics can be formed.
In the resistance element of the present invention, the diffusion region for adjusting the resistance value and the temperature dependent characteristic is formed on the surface side between the contact regions in the well resistance region by the resistance element adjustment method of the present invention. The resistance element can have a desired resistance value and temperature-dependent characteristics.

If the diffusion region in the well resistance region is formed by implanting an impurity having a conductivity type opposite to that of the well resistance region, the resistance value can be reduced and the temperature dependence coefficient can be increased compared to the case where the diffusion region is not formed. .
Further, even if an impurity having the same conductivity type as that of the well resistance region is implanted, the resistance value can be lowered and the temperature dependence coefficient can be increased as compared with the case where the diffusion region is not formed.

  If a silicide layer is formed on the surface side of the diffusion region formed in the well resistance region, the resistance value of the diffusion region is lowered and the resistance value of the resistance element is lowered. Therefore, the conductivity of the diffusion region formed in the well resistance region is reduced. Depending on the combination with the mold, the resistance value and the temperature dependence coefficient can be adjusted in a wide range.

In the conventional technique, for example, when the resistance value of the resistance element is different from a desired resistance value at the time of trial manufacture, the resistance value is adjusted by changing the length or width of the well resistance region. When the well resistance regions are changed, it is necessary to change the mask used for forming them. In order to change these masks, it is necessary to re-form the pattern of the exposure reticle used in the photolithography process, which is troublesome. On the other hand, if the resistance value and temperature-dependent characteristics of the resistance element are adjusted by changing the area ratio of the diffusion region in the well resistance region, the contact region and the contact formation position need not be changed. Therefore, some mask changes for this purpose can be omitted. That is, it is only necessary to change the resistance value formed in the well resistance region and the mask for forming the diffusion region for adjusting the temperature dependence characteristics.
The resistance value and temperature dependence characteristic adjusting method according to the present invention has a resistance value and temperature dependence characteristic in a wider range, particularly by combining the silicide layer on the diffusion region for adjusting the resistance value and the temperature dependence characteristic. Adjustment is possible.

If an element isolation film is formed around the diffusion region in the well resistance region before forming the diffusion region for adjusting the resistance value and the temperature dependence characteristic, the diffusion region forming region is separated from the element. It can be defined by a membrane.
Then, by forming the element isolation film with the STI structure, it is possible to prevent impurities from diffusing outside the formation area of the diffusion area defined by the element isolation film having the STI structure. Can be formed. By doing so, the formation area of the diffusion region for adjusting the resistance value and the temperature dependent characteristic can be controlled with high accuracy, and the adjustment accuracy of the resistance value and the temperature dependent characteristic is improved.

  If the impurity implantation for forming the diffusion region uses a process for forming an element in another region of the same semiconductor substrate, the resistance can be obtained without adding a dedicated process for forming the diffusion region. Values and temperature dependent characteristics can be adjusted.

  In the current generator of the present invention, the temperature dependent characteristic adjusting resistor of the present invention is used as a resistance element, so that a current having a desired temperature dependency can be generated.

1A and 1B are diagrams showing an embodiment of a resistance element made of a well resistor, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA in FIG.
An N-type well resistance region 4 is formed on the main surface side of the P-type semiconductor substrate 2. An element isolation film 12 made of a silicon oxide film having an STI structure is formed around the well resistance region 4.

Contact regions 6, which are high-concentration N ⁺ diffusion regions, are formed at two locations in the well resistance region 4 so as to be separated from each other. A contact 10 made of, for example, tungsten is formed on the contact region 6 via a silicide layer 8.
Between the contact region 6 in the well resistance region 4, a P ⁺ diffusion region 14 for adjusting the resistance value and temperature dependent characteristics of the resistance element is formed. An element isolation film 12 having an STI structure is also formed on the main surface side of a region excluding the contact region 6 and the P ⁺ diffusion region 14 in the well resistance region 4.
The element isolation film 12 may be a LOCOS oxide film formed by a LOCOS method in addition to a silicon oxide film formed with an STI structure.

  Since the diffusion region 14 is formed in the well resistance region 4 in order to adjust the temperature dependency characteristic, the resistance element of this embodiment can have a temperature dependency coefficient corresponding to a circuit using this resistance element. The temperature dependence coefficient has already been described with reference to FIG. 17, but can be adjusted by changing the area ratio occupied by the diffusion region 14 in the well resistance region 4, so that a desired temperature dependence coefficient can be obtained. Further, in order to obtain a desired resistance value, the width or length of the well resistance region has been changed so far, but in the resistance element of this embodiment, the size of the diffusion region 14 in the well resistance region 4 is changed. Since the resistance value can be adjusted only by this, it is not necessary to change the size of the well resistance region 4.

  2 and 3 are cross-sectional process diagrams sequentially illustrating a process of forming the resistance element of FIG. FIG. 3 shows a continuation of FIG.

  (A) A silicon oxide film 16 and a silicon nitride film 18 are formed on the entire main surface of the P-type semiconductor substrate 2. After the entire surface of the silicon nitride film 18 is coated with a resist, a photoresist mask 20 having an opening in a region where an element isolation film is to be formed is formed using photolithography.

  (B) Dry etching is performed using the photoresist mask 20 as a mask to form a rectangular recess having a certain depth in the element isolation film formation region. After the dry etching is completed, the photoresist mask 20 is removed.

  (C) A silicon oxide film 21 is deposited on the entire main surface side of the semiconductor substrate 2 by the CVD method.

  (D) The element isolation film 12 is formed in a rectangular depression formed on the main surface of the semiconductor substrate 2 by polishing, for example, by CMP (Chemical Mechanical Polish).

(E) A photoresist mask 22 having an opening in a region for forming a well resistance region is formed on the main surface of the semiconductor substrate 2 by using a photoengraving technique, and the well resistance region is formed using the photoresist mask 22 as a mask. P (phosphorus), which is an impurity, is ion-implanted into a region for forming. The ion implantation conditions are, for example, a dose of 2 × 10 ¹³ A / cm ² and an output voltage of the ion implanter of 490 KeV. After removing the photoresist mask 22, a thermal diffusion process is performed to form an N-type well resistance region 4.

(F) A photoresist mask 24 having an opening in a region for forming a contact region is formed on the main surface of the semiconductor substrate 2 by using a photolithography technique, and As (arsenic) is formed using the photoresist mask 24 as a mask. Ion implantation. The ion implantation conditions are, for example, a dose of 4 × 10 ¹⁵ A / cm ² and an output voltage of the ion implantation apparatus of 60 KeV. After removing the photoresist mask 24, a thermal diffusion process is performed to form contact regions 6 at both ends of the well resistance region 4.

(G) A photoresist mask 26 having an opening in a region where a P ⁺ diffusion region is to be formed is formed on the main surface of the semiconductor substrate 2 using photolithography. For example, B (boron) is ion-implanted as an impurity using the photoresist mask 26 as a mask. The ion implantation conditions are, for example, a dose amount of 2.5 × 10 ¹⁵ A / cm ² and an output voltage of the ion implantation apparatus of 5 KeV.

(H) After removing the photoresist mask 26, a thermal diffusion process is performed to form the P ⁺ diffusion region 14 between the contact regions 6 on the surface side of the well resistance region 4.
Thereafter, the silicide layer 8 and the contact 10 are formed on the contact region 6 to complete the resistance element shown in FIG.

  The steps (a) to (h) are shown as dedicated steps for forming a resistance element. For example, ion implantation in steps (f) and (g) is performed for transistors formed in other regions. An ion implantation process for forming the source and drain can be used. Then, the resistance value and the temperature dependence characteristic can be adjusted without adding a new process to the conventional process of forming the resistance element.

In the formation process of this embodiment, the element isolation film 12 is formed with the STI structure using the CVD method and the CMP method. However, the present invention is not limited to this, and the LOCOS oxide film is formed using the LOCOS method. May be formed as the element isolation film 12. However, in the process after the element isolation film 12 is formed, the impurities implanted to form the contact region 6 and the P ⁺ diffusion region 14 are reliably prevented from diffusing outside the desired formation region. More preferably, the element isolation film 12 is formed with an STI structure.

FIGS. 4A and 4B are diagrams showing another embodiment of a resistance element made of a well resistor, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view at a BB position in FIG.
In the resistance element of this embodiment, an N-type well resistance region 4 is formed on the main surface side of a P-type semiconductor substrate 2. An element isolation film 12 made of a silicon oxide film having an STI structure is formed around the well resistance region 4, and the well resistance region 4 is electrically isolated from other elements. Contact regions 6, which are high-concentration N ⁺ diffusion regions, are formed at two locations in the well resistance region 4 so as to be separated from each other. A contact 10 made of, for example, tungsten is formed on the contact region 6 via a silicide layer 8.

In the region between the contact regions 6 in the well resistance region 4, an N ⁺ diffusion region 34 for adjusting the resistance value and temperature dependent characteristics of the resistance element is formed. In the resistance element of FIG. 1, the P ⁺ diffusion region 14 is formed in order to decrease the resistance value of the well resistance region 4 and increase the temperature dependence coefficient. However, the resistance element of this embodiment has the same N ⁺ diffusion region 34. Formed in the region. By forming the N ⁺ diffusion region 34 instead of the P ⁺ diffusion region 14, the resistance value of the resistance element can be further reduced. In such a resistance element, by changing the proportion of the N ⁺ diffusion region 34 in the well resistance region 4, the resistance value and temperature dependent characteristics of the resistance element can be adjusted, and the proportion of the N ⁺ diffusion region 34 is occupied. As the value increases, the resistance value decreases.

  The resistance element of FIG. 4 can be formed by sequentially performing the following steps (a) to (e), (f ′), and (h ′). Steps (a) to (e) correspond to (a) to (e) in FIG. 2, and (f ′) and (h ′) correspond to (f ′) and (h ′) in FIG. .

  (A) A silicon oxide film 16 and a silicon nitride film 18 are formed on the entire main surface of the P-type semiconductor substrate 2. A photoresist mask 20 having an opening in a region where an element isolation film is to be formed is formed on the silicon nitride film 18 using photolithography.

  (B) Dry etching is performed using the photoresist mask 20 as a mask to form a rectangular recess having a certain depth in the element isolation film formation region. After the dry etching is completed, the photoresist mask 20 is removed.

  (C) A silicon oxide film 21 is deposited on the entire main surface side of the semiconductor substrate 2 by the CVD method.

  (D) The element isolation film 12 is formed in a rectangular recess formed on the main surface of the semiconductor substrate 2 by polishing, for example, by CMP.

(E) A photoresist mask 22 having an opening in a region for forming a well resistance region is formed on the main surface of the semiconductor substrate 2 by using a photoengraving technique, and the well resistance region is formed using the photoresist mask 22 as a mask. P (phosphorus), which is an impurity, is ion-implanted into a region for forming. The ion implantation conditions are, for example, a dose of 2 × 10 ¹³ A / cm ² and an output voltage of the ion implanter of 490 KeV. After removing the photoresist mask 22, a thermal diffusion process is performed to form an N-type well resistance region 4.

(F ′) A photoresist mask 36 having openings in the formation region of the contact region 6 and the formation region of the N ⁺ diffusion region 34 is formed on the main surface of the semiconductor substrate 2 on which the well resistance region 4 is formed. Impurity As is ion-implanted using the resist mask 36 as a mask. The ion implantation conditions are, for example, a dose of 4 × 10 ¹⁵ A / cm ² and an output voltage of the ion implantation apparatus of 60 KeV.

(H ′) After removing the photoresist mask 36, a thermal diffusion process is performed to form the contact region 6 and the N ⁺ diffusion region 34.
Thereafter, a silicide layer 8 and a contact 10 are formed on the contact region 6 to complete the resistance element shown in FIG.

In the formation process of this embodiment, the element isolation film 12 is formed with the STI structure using the CVD method and the CMP method. However, the present invention is not limited to this, and the LOCOS oxide film is formed using the LOCOS method. May be formed as the element isolation film 12. However, in the process after the element isolation film 12 is formed, the impurities implanted to form the contact region 6 and the P ⁺ diffusion region 14 are reliably prevented from diffusing outside the desired formation region. More preferably, the element isolation film 12 is formed with an STI structure.

Next, still another embodiment of the resistance element will be described. 6A and 6B are diagrams showing still another embodiment of the resistance element, in which FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along the line CC in FIG.
In this resistance element, an N-type well resistance region 4 electrically isolated by an element isolation film 12 is formed on the main surface side of the semiconductor substrate 2 in the same manner as the resistance element of FIG. Contact regions 6 are formed at two locations in the well resistance region 4 so as to be separated from each other. A contact 10 made of, for example, tungsten is formed on the contact region 6 via a silicide layer 8.
An N ⁺ diffusion region 34 is formed between the contact region 6 in the well resistance region 4 for adjusting the resistance value and temperature dependent characteristics of the resistance element. On the surface side of the N ⁺ diffusion region 34, a silicide layer 28 formed by reacting, for example, Co (cobalt) and silicon is formed. In the well resistance region 4 except for the region where the contact region 4 and the N ⁺ diffusion region 34 are formed, an element isolation film 12 having an STI structure is formed.

  A method for forming the resistance element of FIG. 6 will be described. The resistance element of FIG. 6 can be formed by sequentially performing the following steps (a) to (e), (f ′), (h ′), and (i) to (l). The following steps (a) to (e) correspond to (a) to (e) in FIG. 2, and steps (f ′) and (h ′) correspond to (f ′) and (h ′) in FIG. Steps (i) to (l) correspond to (i) to (l) in FIG.

  (A) A silicon oxide film 16 and a silicon nitride film 18 are formed on the entire main surface of the P-type semiconductor substrate 2. After the entire surface of the silicon nitride film 18 is coated with a resist, a photoresist mask 20 having an opening in a region where an element isolation film is to be formed is formed using photolithography.

  (B) Dry etching is performed using the photoresist mask 20 as a mask to form a rectangular recess having a certain depth in the element isolation film formation region. After the dry etching is completed, the photoresist mask 20 is removed.

  (C) A silicon oxide film 21 is deposited on the entire main surface side of the semiconductor substrate 2 by the CVD method.

  (D) The element isolation film 12 is formed in a rectangular recess formed on the main surface of the semiconductor substrate 2 by polishing, for example, by CMP.

(E) A photoresist mask 22 having an opening in a region for forming a well resistance region is formed on the main surface of the semiconductor substrate 2 by using a photoengraving technique, and the well resistance region is formed using the photoresist mask 22 as a mask. P (phosphorus), which is an impurity, is ion-implanted into a region for forming. The ion implantation conditions are, for example, a dose of 2 × 10 ¹³ A / cm ² and an output voltage of the ion implanter of 490 KeV. Thereafter, the photoresist mask 22 is removed, and thermal diffusion treatment is performed to form an N-type well resistance region 4.

(F ′) A photoresist mask 36 having openings in the formation region of the contact region 6 and the formation region of the N ⁺ diffusion region 34 is formed on the main surface of the semiconductor substrate 2 using a photoengraving technique. For example, As is ion-implanted as an impurity using the photoresist mask 36 as a mask. The ion implantation conditions are, for example, a dose of 4 × 10 ¹⁵ A / cm ² and an output voltage of the ion implantation apparatus of 60 KeV.

(H ′) After removing the photoresist mask 36, a thermal diffusion process is performed to form the contact region 6 and the N ⁺ diffusion region 34.

(I) A silicon oxide film 30 is formed on the entire main surface of the semiconductor substrate 2, and a photoresist mask 32 having openings on the contact region 6 and the N ⁺ diffusion region 34 is formed on the silicon oxide film 30 by photolithography. Use to form.

(J) Etching is performed using the photoresist mask 32 as a mask, the silicon oxide film 30 on the contact region 6 and the N ⁺ diffusion region 14 is removed, and the photoresist mask 32 is further removed.

  (K) A refractory metal film 33 such as Co (cobalt) is formed on the entire main surface of the semiconductor substrate 2. As the refractory metal film 33, any metal that can be used for a method of forming a silicide layer in a self-aligned manner generally called salicide, such as Ti (titanium) and Ni (nickel), in addition to Co can be used.

(L) Heat treatment is performed to react the refractory metal 33 and silicon in contact with the refractory metal 33 to form the silicide layer 8 on the contact region 6 and the silicide layer 28 on the N ⁺ diffusion region 34. Thereafter, the unreacted refractory metal film 33 is removed.
By forming the contact 10 on the silicide layer 8 on the contact region 6, the resistance element of FIG. 6 is completed.

In this embodiment, the silicide layer 28 is formed on the N ⁺ diffusion region 34 for adjusting the resistance value and the temperature dependence characteristic, thereby reducing the resistance value of the N ⁺ diffusion region 34. As described above, not only the area ratio of the diffusion region for adjusting the resistance value and the temperature-dependent characteristic in the well resistance region is changed, but also a silicide layer is formed on the diffusion region for adjusting the resistance value and the temperature-dependent characteristic. The resistance value can be adjusted more widely.
Further, as shown in the formation steps (i) to (l), the step of forming the silicide layer 8 on the contact region 6 is used as the step of forming the silicide layer 28 on the N ⁺ diffusion region 34. Therefore, the resistance value can be reduced without increasing the number of steps.

In this embodiment, the step of forming the silicide layer 8 on the contact region 6 is used as the step of forming the silicide layer 28 on the N ⁺ diffusion region 34, but the present invention is limited to this. Instead of this, a silicide layer 28 may be formed on the N ⁺ diffusion region 34 by adding a step separately from the step of forming the silicide layer 8 on the contact region 6. Although illustration and detailed explanation are omitted, the P ⁺ is also applied to the resistance element in which the P ⁺ diffusion region is formed as the diffusion region for adjusting the resistance value and the temperature dependence characteristic as shown in FIG. A silicide layer may be formed on the diffusion region.

In the formation process of this embodiment, the element isolation film 12 is formed with the STI structure using the CVD method and the CMP method. However, the present invention is not limited to this, and the LOCOS oxide film is formed using the LOCOS method. May be formed as the element isolation film 12. However, in the process after the element isolation film 12 is formed, the impurities implanted for forming the contact region 6 and the N ⁺ diffusion region 34 are reliably prevented from diffusing outside the desired formation region. More preferably, the element isolation film 12 is formed with an STI structure.

Next, an embodiment of a resistance element composed of two well resistance regions will be described. FIGS. 9A and 9B are diagrams showing an embodiment of a resistance element composed of two well resistance regions. FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along the line EE in FIG.
In the resistance element of this embodiment, two N-type well resistance regions 4a and 4b electrically separated by the element isolation film 44 are formed at two positions on the main surface side of the P-type semiconductor substrate 2 so as to be separated from each other. Has been. The element isolation film 44 may be a LOCOS oxide film formed by the LOCOS method in addition to the STI structure shown in the drawing.

Contact regions 6a, which are high-concentration N ⁺ diffusion regions, are formed at two locations in the well resistance region 4a so as to be separated from each other, and contacts 10a made of, for example, tungsten are formed on the contact region 6a via the silicide layer 8a. Has been. Between the contact regions 6a spaced apart from each other, an N ⁺ diffusion region 46 for adjusting a resistance value and a temperature dependent characteristic is formed.

Contact regions 6b, which are high-concentration N ⁺ diffusion regions, are formed at two locations in the well resistance region 4b so as to be separated from each other, and contacts 10b made of, for example, tungsten are formed on the contact region 6b via the silicide layer 8b. Has been. Between the contact regions 6b spaced apart from each other, a P ⁺ diffusion region 48 for adjusting the resistance value and the temperature dependent characteristic is formed. On the surface side of the P ⁺ diffusion region 48, a silicide layer 50 made of, for example, Co and silicon is formed.

The region other than the contact region 6a and the N ⁺ diffusion region 46 of the well resistance region 4a, and the region other than the contact region 6b and the P ⁺ diffusion region 48 of the well resistance region 4b are formed around the well resistance regions 44 and 46. The same element isolation film 48 as the element isolation film 48 is formed.

  Next, a method for forming the resistance element shown in FIG. 9 will be described with reference to FIGS. 10 and 11 are process cross-sectional views sequentially showing the process of forming the resistance element, and FIG. 11 shows a continuation of FIG.

  (A) A silicon oxide film 52 and a silicon nitride film 54 are formed on the entire main surface of the P-type semiconductor substrate 2. Further, a photoresist mask 56 having an opening in a region where an element isolation film is to be formed is formed on the silicon nitride film 54 using a photoengraving technique.

  (B) Dry etching is performed using the photoresist mask 56 as a mask to form a rectangular recess having a certain depth in the element isolation film formation region. After the dry etching is completed, the photoresist mask 56 is removed.

  (C) A silicon oxide film 58 is deposited on the entire main surface side of the semiconductor substrate 2 by the CVD method.

  (D) The element isolation film 44 is formed in a rectangular recess formed on the main surface of the semiconductor substrate 2 by polishing, for example, by CMP.

(E) A photoresist mask 60 having an opening in a region for forming a well resistance region is formed on the main surface of the semiconductor substrate 2 by using a photoengraving technique, and the well resistance region is formed using the photoresist mask 60 as a mask. P (phosphorus) is ion-implanted into the region where the film is formed. The ion implantation conditions are, for example, a dose of 2 × 10 ¹³ A / cm ² and an output voltage of the ion implanter of 490 KeV. After removing the photoresist mask 60, a thermal diffusion process is performed to form N-type well resistance regions 4a and 4b.

(F) Photoresist engraving technique is used to form a photoresist mask 62 having an opening in a region for forming the contact region of the well resistance regions 4a and 4b and a region for forming an N ⁺ diffusion region for adjusting the resistance value and temperature-dependent characteristics. And formed on the main surface of the semiconductor substrate 2. As (arsenic) ions are implanted using the photoresist mask 62 as a mask. The ion implantation conditions are, for example, a dose of 4 × 10 ¹⁵ A / cm ² and an output voltage of the ion implantation apparatus of 60 KeV. Thereafter, the photoresist mask 62 is removed, and thermal diffusion processing is performed to form contact regions 6a and 6b and an N ⁺ diffusion region 46.

(G) A photoresist mask 64 having an opening in a region where the P ⁺ diffusion region of the well resistance region 4b is to be formed is formed on the main surface of the semiconductor substrate 2 using photolithography. B (boron) ions are implanted using the photoresist mask 64 as a mask. The ion implantation conditions are, for example, a dose amount of 2.5 × 10 ¹⁵ A / cm ² and an output voltage of the ion implantation apparatus of 5 KeV. Thereafter, the photoresist mask 26 is removed, and a thermal diffusion process is performed to form a P ⁺ diffusion region 48 between the contact regions 6b.

(H) A silicon oxide film 66 is formed on the entire main surface of the semiconductor substrate 2 and an opening is formed in the region where the silicide layer is to be formed thereon, here on the contact regions 6a and 6b and on the P ⁺ diffusion region 48. Then, dry etching is performed using the resist mask as a mask to leave the silicon oxide film 66 only in the region where the silicide layer is not formed, that is, on the N ⁺ diffusion region 46.

  (I) A refractory metal film 68 made of, for example, Co is formed on the entire surface of the semiconductor substrate 2 including the silicon oxide film 66. As the refractory metal film 68, any metal that can be used in a method of forming a silicide layer in a self-aligned manner generally called salicide, such as Ti (titanium) and Ni (nickel), in addition to Co can be used.

(J) By heat treatment, the refractory metal film 68 reacts with silicon in contact with the refractory metal film 68 to form silicide layers 8a and 8b on the contact regions 6a and 6b, and on the P ⁺ diffusion region 48. A silicide layer 50 is formed. Unreacted refractory metal film 68 is removed.
Thereafter, contacts 10a and 10b are formed on the silicide layers 8a and 8b on the contact regions 6a and 6b, thereby completing the resistance element shown in FIG.

In the formation step, for example, the ion implantation step for forming the N ⁺ diffusion region 46 in the step (f) and the ion implantation step for forming the P ⁺ diffusion region 48 in the step (g) are performed in addition to the semiconductor substrate 2. A process for forming the source, drain, and other diffusion layers of the CMOS transistor formed in this region can be used. In this case, since a dedicated process for forming the diffusion regions 46 and 48 is not required, the resistance value and the temperature dependence characteristics can be adjusted without adding a new process to the conventional forming process.

In the formation process of this embodiment, the element isolation film 44 is formed with the STI structure using the CVD method and the CMP method. However, the present invention is not limited to this, and the LOCOS method is used for the LOCOS method. An oxide film may be formed as the element isolation film 44. However, the impurities implanted to form the contact regions 6a and 6b, the N ⁺ diffusion region 46 or the P ⁺ diffusion region 48 in the process after the formation of the element isolation film 12 are diffused outside the desired formation region. In order to surely prevent this, it is more preferable to form the element isolation film 44 with an STI structure.

An embodiment of the current generator of the present invention will be described.
As an application of the resistance element having the resistance value and temperature dependency characteristics adjusted as shown in the above embodiment, for example, a constant current circuit as an embodiment of a current generator as shown in FIG. Can do.

The constant current circuit of FIG. 12 will be described.
M1, M2 and M3 are the same pair MOS transistors connected in a current mirror, and the sources of the transistors M1, M2 and M3 are connected to the power supply circuit via the power supply terminal 38. The transistor M1 is grounded via the bipolar transistor Q1, and the transistor M2 is grounded via the resistor R and the bipolar transistor Q2. The bases and collectors of the bipolar transistors Q1 and Q2 are grounded. Bipolar transistors Q1 and Q2 have the same characteristics, but have different base-emitter areas.

A potential due to the collector-emitter voltage of the bipolar transistor Q1 is input to the inverting input terminal (−terminal) of the operational amplifier 44, and the base-emitter voltage and resistance of the bipolar transistor Q2 are input to the non-inverting input terminal (+ terminal). A potential due to the voltage applied to both ends of R is input.
In this constant current circuit, the transistors M1 and M2, the bipolar transistors Q1 and Q2, and the operational amplifier 44 constitute a voltage generation unit that generates a voltage having a specific dependence on a temperature change in the current generator of the present invention. The resistor R constitutes a resistance element to which the voltage generated by the voltage generation unit is applied at both ends, and the transistor M3 outputs a current corresponding to the voltage generated by the voltage generation unit and the temperature characteristics of the resistance element. The output unit is configured.

  In such a constant current circuit, the temperature dependence coefficient TC (I) of the reference current I is determined by the difference between TC (Vt) and TC (R), as shown in the above-described equation (2). . As the resistor R, for example, a resistor element in which a diffusion region for adjusting a resistance value and temperature-dependent characteristics is formed in a well resistor region as shown in FIG. 1, FIG. 4, FIG. 6, or FIG. Thus, the temperature dependence coefficient TC (R) can be adjusted, and the temperature dependence characteristics of the reference current I can be adjusted. In this constant current circuit, in the well resistance region of the resistor R, for example, a diffusion region for adjusting the resistance value and the temperature dependence characteristic is formed as shown in FIG. 1, FIG. 4, FIG. 6 or FIG. If the temperature dependence of Vt is canceled by the temperature dependence of the resistor R, the temperature dependence of the reference current I can be reduced, and the output current I can be made constant regardless of the temperature change.

FIG. 13 is a graph showing the relationship between the temperature (° C.) and the reference current I (μA) in the constant current circuit of FIG. In (A), the horizontal axis is temperature (° C.), and the vertical axis is current I (μA). In (B), the horizontal axis represents temperature (° C.), and the vertical axis represents current fluctuation rate (%). The current fluctuation rate here is based on the output current value when the temperature is 25 ° C. In (A) and (B), a graph a indicated by a thick solid line indicates a resistance R as a P ⁺ diffusion region 14 having a large area in the well resistance region 4, as shown in FIG. , A resistance element in which a P ⁺ diffusion region of 70 μm × 4 μm is formed in the well resistance region 4 of 80 μm × 6 μm is used. Further, a graph b occupied by a solid line thinner than the graph a is a resistance R, as shown in FIG. 1, a P ⁺ diffusion region 14 having a smaller area than that of FIG. Specifically, a resistance element in which a P ⁺ diffusion region of 35 μm × 4 μm is formed in a well resistance region 4 of 75 μm × 6 μm is used. A graph c indicated by a broken line is a case where a resistance element in which a diffusion region for adjusting temperature-dependent characteristics is not formed in the well resistance region 4 is used as the resistance R, as shown in FIG. The temperature dependence coefficient of the resistance element used in graph a is 3963 ppm / ° C., the temperature dependence coefficient of the resistance element used in graph b is 3734 ppm / ° C., and the temperature dependence coefficient of the resistance element used in graph c is 3439 ppm / ° C. there were.

From these graphs (A) and (B), in the graph of c in which the resistance element has a conventional structure, the reference current I fluctuates in the range of 0.94 μA to 1.06 μA due to temperature change, and the output at 25 ° C. The rate of change based on the current value fluctuated in the range of −10% to + 2%, with a maximum variation of 12%. On the other hand, in the graph of a in which the P ⁺ diffusion region 14 is widely formed in the well resistance region 4, the reference current I fluctuates in the range of 1 μA to 1.05 μA due to temperature change, and the variation rate based on 25 ° C. Fluctuated in the range of -5.5% to 0%, and there was only a variation of 5.5% at the maximum. Also in the graph of b, the reference current I fluctuates in the range of 0.99 μA to 1.07 μA, and the fluctuation rate based on 25 ° C. fluctuates in the range of −7.5% to + 0.5%. The maximum variation was only 8%.

  Therefore, if a diffusion region for adjusting the temperature dependence characteristic is formed in the well resistance area of the resistance element, the resistance value and the temperature dependence characteristic of the resistance element are adjusted to satisfy the requirements of the circuit, and used as the resistance R, a wide range It is possible to configure a circuit that can output a stable current even when the temperature changes.

Table 1 shows the results of evaluating the resistance value and the temperature dependence coefficient (TCR) of the N-type well resistance region 4 provided with the element isolation film having the STI structure.
14A and 14B are diagrams showing a schematic structure of a sample used for the evaluation. FIG. 14A is a sectional view of a conventional technique, FIG. 14B is a sectional view of a structure including an N ⁺ diffusion region 34, and FIG. ⁺ A cross-sectional view of a structure provided with a diffusion region 14, (D) is a plan view showing a layout. The conditions for forming the N-type well resistance region 4, the P ⁺ diffusion region 14, and the N ⁺ diffusion region 34 are the same as those in the above embodiment. In these samples, the width of the N-type well resistance region 4 was 6 μm, and the size between the contact regions 6 and 6 was 60 μm. Further, the length dimension of the P ⁺ diffusion region 14 and the N ⁺ diffusion region 34 was 58 μm, and the width dimension was 4 μm. The depth of the element isolation film 12 was made deeper than the junction position of the N-type well resistance region 4 and the P ⁺ diffusion region 14 or the N ⁺ diffusion region 34.

As can be seen from Table 1, the structure (B) including the N ⁺ diffusion region 34 and the structure (C) including the P ⁺ diffusion region 14 can lower the resistance value as compared with the structure (A) of the prior art. . This is because the element isolation film 12 having the STI structure is formed deeper than the junction position of the N-type well resistance region 4 and the P ⁺ diffusion region 14 or the N ⁺ diffusion region 34.
Both the temperature dependence coefficient (TCR) of the structure (B) having the N ⁺ diffusion region 34 and the structure (C) having the P ⁺ diffusion region 14 are larger than those of the structure (A) of the prior art.

Table 2 shows the evaluation results of the resistance value and the temperature dependence coefficient (TCR) of the N-type well resistance region 4 provided with the element isolation film made of the LOCOS oxide film.
15A and 15B are diagrams showing a schematic structure of a sample used for the evaluation. FIG. 15A is a cross-sectional view of the prior art, FIG. 15B is a cross-sectional view of a structure including an N ⁺ diffusion region 34, and FIG. ⁺ A cross-sectional view of a structure provided with a diffusion region 14, (D) is a plan view showing a layout. The conditions for forming the N-type well resistance region 4, the P ⁺ diffusion region 14, and the N ⁺ diffusion region 34 are the same as those in the above embodiment. In these samples, the width dimension of the N-type well resistance region 4 was 2 μm, and the dimension between the contact regions 6 and 6 was 300 μm. Further, the length dimension of the P ⁺ diffusion region 14 and the N ⁺ diffusion region 34 is 298.8 μm, and the width dimension is 2 μm, the same as the width dimension of the N-type well resistance region 4. The depth of the element isolation film 13 was made shallower than the junction position of the N-type well resistance region 4 and the P ⁺ diffusion region 14 or the N ⁺ diffusion region 34.

As can be seen from Table 2, the resistance value can be lowered in the structure (B) including the N ⁺ diffusion region 34 as compared with the structure (A) of the prior art. On the other hand, the resistance value can be increased in the structure (C) including the P ⁺ diffusion region 14 as compared with the structure (A) of the prior art. This is because the junction depth between the N-type well resistance region 4 and the P ⁺ diffusion region 14 is formed to be deeper than the depth of the element isolation film 13 made of the LOCOS oxide film. It is presumed that the depth dimension (the dimension between the bottom surface of the P ⁺ diffusion region 14 and the bottom surface of the N-type well resistance region 4) is smaller than that of the prior art structure (A) and the resistance value is increased.
In addition, the temperature dependency coefficient (TCR) of the structure (B) including the N ⁺ diffusion region 34 and the structure (C) including the P ⁺ diffusion region 14 are both smaller than the structure (A) of the prior art.

  In general, the temperature dependence coefficient of the N-type well resistance used in the constant current circuit is preferably about 4000 ppm / ° C. In the case of an N-type well resistor having an element isolation film made of a LOCOS oxide film, the temperature dependency coefficient of the structure of the prior art (about 6000 ppm / ° C., see the conventional structure (A) in Table 2) is too high. To complement this, a P-type well resistance having a small temperature dependence coefficient (temperature dependence coefficient is about 1700 ppm / ° C.) or the like is used in combination with an N-type well resistance to comprehensively achieve a target temperature dependence coefficient (4000 ppm / ° C. ) Was achieved.

As described with reference to Table 2 and FIG. 15, in the structure (C) in which the N type well resistance region 4 includes the P ⁺ diffusion region 14, the resistance value can be increased as compared with the structure (A) of the prior art. Therefore, by using a structure having a P ⁺ diffusion region in the N-type well resistance region, the length of the resistance region can be shortened compared to the prior art when obtaining a desired resistance value, and the layout can be reduced. Can be small.
Further, in the structure having the P ⁺ diffusion region in the N-type well resistance region, the temperature dependence coefficient can be made smaller than that of the prior art (see Table 2 and FIG. 15), so that it is used to complement the temperature dependence coefficient. The resistance element can also be reduced.

  In the embodiments in the present specification, the N-type well resistance region 4 is formed in the P-type semiconductor substrate 2, but the present invention is not limited to this, and all are of the opposite conductivity type. May be.

It is a figure which shows one Example of a resistive element, (A) is a top view, (B) is sectional drawing in the AA position of (A). FIG. 3 is a process cross-sectional view sequentially illustrating a formation process for forming the resistance element of FIG. 1. FIG. 3 is a process cross-sectional view illustrating the continuation of FIG. 2. It is a figure which shows other Example of a resistive element, (A) is a top view, (B) is sectional drawing in the BB position of (A). FIG. 5 is a process cross-sectional view illustrating a continuation of FIG. 2 in a formation process for forming the resistance element of FIG. 4. It is a figure which shows other Example of a resistive element, (A) is a top view, (B) is sectional drawing in CC position of (A). FIG. 6 is a process cross-sectional view subsequent to FIG. 5, illustrating additional processes for forming the resistance element of FIG. 6 in order. It is a figure which shows other Example of a resistive element, (A) is a top view, (B) is sectional drawing in the DD position of (A). It is a figure which shows other Example of a resistive element, (A) is a top view, (B) is sectional drawing in the EE position of (A). FIG. 10 is a process cross-sectional view sequentially illustrating a process of forming the resistance element of FIG. 9. FIG. 11 is a process cross-sectional view illustrating the continuation of FIG. 10. It is a circuit diagram which shows an example of a structure of a constant current circuit. FIG. 13 is a diagram illustrating a relationship between a temperature and a reference current in the constant current circuit of FIG. 12, wherein (A) is a graph of temperature-reference current I, and (B) is a graph of temperature-current variation rate. It is a figure which shows schematic structure of the sample used for evaluation of the resistance value of a N-type well resistance area | region provided with the element isolation film of STI structure, and a temperature dependence coefficient, (A) is sectional drawing of a prior art, (B) is N ⁺ cross-sectional view of the structure with the diffusion region, (C) is a sectional view of the structure with a P ⁺ diffusion region, (D) is a plan view showing a layout. It is a figure which shows schematic structure of the sample used for evaluation of the resistance value and temperature dependence coefficient of an N-type well resistance area | region provided with the element isolation film which consists of a LOCOS oxide film, (A) is sectional drawing of a prior art, (B) Is a cross-sectional view of a structure having an N ⁺ diffusion region, (C) is a cross-sectional view of a structure having a P ⁺ diffusion region, and (D) is a plan view showing a layout. It is a figure which shows an example of the conventional resistive element, (A) is a top view, (B) is sectional drawing in the FF position of (A). It is a graph which shows the relationship between the area ratio which the P ^<+> diffusion area | region occupies in a well resistance area | region, and a temperature dependence coefficient.

Explanation of symbols

2 Semiconductor substrate 4 Well resistance region 6 Contact region 8, 28 Silicide layer 10 Contact 12 Element isolation film 14 P ⁺ diffusion region 34 N ⁺ diffusion region

Claims (16)

A method of adjusting a resistance value and temperature-dependent characteristics of a resistance element including a well resistance region formed in a semiconductor substrate and contact regions formed in the well resistance region so as to be separated from each other,
A resistance element adjusting method comprising: forming a diffusion region for adjusting a resistance value and a temperature-dependent characteristic on a surface side between the contact regions in the well resistance region. The resistance element adjusting method according to claim 1, wherein the diffusion region is formed by implanting an impurity having a conductivity type opposite to that of the well resistance region. The resistance element adjusting method according to claim 1, wherein an impurity having the same conductivity type as that of the well resistance region is implanted to form the diffusion region. The resistance element adjusting method according to claim 1, wherein a silicide layer is formed on a surface side of the diffusion region. The resistance element adjustment method according to claim 1, wherein the resistance value and the temperature-dependent characteristic are adjusted by changing an area ratio of the diffusion region in the well resistance region. 6. The resistance element adjusting method according to claim 1, wherein an element isolation film is formed around a region of the well resistance region where the diffusion region is formed before the diffusion region is formed. The element isolation film is formed by etching a semiconductor substrate in a formation region thereof to form a depression, and after forming an insulating film on the semiconductor substrate including the depression by a deposition method, only the depression is formed by a planarization process. The resistance element adjusting method according to claim 6, wherein the insulating film is left on the insulating film. 8. The resistance element adjusting method according to claim 7, wherein the well resistance region is formed by implanting impurities after forming the element isolation film. The resistance element adjusting method according to claim 1, wherein the impurity implantation for forming the diffusion region uses a process for forming an element in another region of the semiconductor substrate. A resistor comprising a well resistance region formed on the main surface side of the semiconductor substrate, a contact region formed in two regions spaced apart from each other in the well resistance region, and a contact formed on the contact region In the element
A resistance element, wherein a diffusion region for adjusting a resistance value and a temperature dependent characteristic is formed on a surface side of a region between the contact regions of the well resistance region. The resistance element according to claim 10, wherein the diffusion region has a conductivity type opposite to that of the well resistance region. The resistance element according to claim 10, wherein the diffusion region has the same conductivity type as the well resistance region. The resistance element according to claim 10, wherein an element isolation film is formed in a region different from the contact region and the diffusion region of the well resistance region. The resistance element according to claim 13, wherein the element isolation film is an insulating film embedded in a recess formed in the semiconductor substrate. 15. The resistance element according to claim 10, further comprising a plurality of well resistance regions, wherein a diffusion region for adjusting a resistance value and temperature dependent characteristics is formed in at least one of the well resistance regions. A voltage generation unit that generates a voltage having a specific dependence on a temperature change; a resistance element to which a voltage generated by the voltage generation device is applied at both ends; and a temperature characteristic of each of the voltage and the resistance element In a current generator having a current output unit that outputs a current according to
16. A current generator, wherein the resistance element for temperature characteristic adjustment according to claim 10 is used as the resistance element.

Images