JP3983751B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a salicide (SALICIDE: Self Aligned Silicide) technique and a method for manufacturing the same.
About.

  In recent years, in semiconductor devices, gate electrodes have been miniaturized in order to improve the digital operation speed. Then, the miniaturization of the manufacturing process has progressed, and nowadays, semiconductor devices are generally manufactured using salicide technology. In the salicide technology, for example, the surface of a silicon material such as polysilicon which is a gate electrode material of a transistor or a diffusion layer which becomes a source region and a drain region is coated with a refractory metal such as titanium (Ti) or cobalt (Co). This is a technique for reducing the resistance value of polysilicon or a diffusion layer by forming a silicide layer in a self-aligning manner.

  On the other hand, as represented by power supply products, analog applications are also increasing. In particular, regarding analog characteristics, since variations in resistance and capacitance influence circuit characteristics, variations that can be ignored in digital circuits are also very important.

  As described above, in the miniaturization of the manufacturing process, for example, in the process of 0.25 μm and later, the salicide technique is used to reduce the resistance value of the polysilicon and the diffusion layer. However, in a circuit using high resistance, such as an analog resistance element, if a resistor to which salicide technology is applied (hereinafter referred to as salicide resistor) is used, a large area is required to form a desired resistor. For this reason, a region where no salicide is required, for example, a portion where a high resistance is required is masked to form a region where a silicide layer is not formed. By removing the refractory metal on the surface using a layout mask pattern that masks a portion other than the portion where the value is required, an area that is not salicided is created as necessary. Hereinafter, these areas are referred to as an answer side area. In a circuit using a high resistance, this unsalicide region is used as a resistance. The resistance using this unsalicide region is called an unsalicide resistance.

  The use of such an answer side region as a resistor having a high resistance is described in, for example, Patent Document 1.

  As described above, in order to form the answer side region, it is necessary to create a mask. If there is a variation in the photographic process at the time of creating a mask for forming the unsalicide region, this results directly in variations in the unsalicide resistance.

  Since the mask for forming the unsalicide region does not require fine processing such as a polysilicon gate or a contact, it is often handled as a rough layer, and the size is often not controlled. Also, there are various patterns from large to small. Especially for large patterns, shrinkage during photoresist development is likely to occur, and resistance values are likely to vary. Therefore, particularly in an analog circuit using an unsalicide resistor, desired characteristics are often not obtained due to such photographic process variations.

  An example in which the resistance value varies will be described with reference to FIG. FIG. 14 is a plan view showing a layout of a conventional answer-side diffused resistor. Shown are a diffusion region 201, a mask 202 for forming an unsalicide region, and a contact 203. Here, the answer-side diffusion resistance is described as the answer-side resistance, but the same applies to the polysilicon resistance.

FIG. 14 (a) shows the answer resistance formed as designed. FIG. 14B shows a photographic process for creating a mask for forming an unsalicide region, and shows a case where a large amount of exposure has been completed or a shrinkage (shrinkage) of the resist has occurred. This shows a case where the mask becomes smaller. (C) of FIG. 14 shows a case where the exposure amount is small and the mask for forming the salicide side region is large in the photographic process for creating the mask for forming the salicide side region, contrary to (b). ing.
JP 2000-269338 A

  As can be seen from FIG. 14 above, the width of the answer side region is determined by the diffusion region as the lower layer, but the length direction is determined by the mask for forming the answer side region, and due to variations in the photographic process. The length direction is greatly different.

  As described above, since the mask for forming the unsalicide region has a high possibility of variation, the resistance value is highly likely to vary greatly. For this reason, there is a problem that the characteristics deteriorate when used in an analog circuit having severe resistance variation.

  The present invention has been made in view of the above-described conventional problems, and is capable of reducing variations in high resistance ansalicide resistance values even if there are variations in the photographic process when forming the mask for forming the unsalicide regions. Objective.

The semiconductor device of this invention, in a semiconductor device including a resistive element that is not a semiconductor element and Salicided which is Risaido of the resistance element, the thickness towards at least the width of the end portion terminating includes a contact region Kunar together are formed as a region to part of the portion of varying width comprising a pre SL contact region from the end portion is salicided, other parts are characterized by non-salicided.

  The resistive element is composed of a rectangular region and a region that is connected to the rectangular region so that the width of the terminal portion increases toward the terminal, and the resistive element is a rectangular region. And a region formed such that the width of the terminal portion is continuous with the rectangular region and becomes thicker in a tapered shape toward the terminal.

The method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device including a resistive element that is not a semiconductor element and Salicided that are salicided, width of at least end portion including the contact regions rather thick toward the end After forming the salicide block region including at least the contact region and reaching a part of the portion where the width of the resistance region changes, the resistor region is formed. A salicided region and a non-salicided region are formed.

  According to the present invention, the resistance element is formed so that at least the width of the terminal portion becomes thicker toward the terminal end, and a portion of the portion where the width changes is salicided, so that the salicide block region is not displaced. Even if it occurs, variation in resistance value can be suppressed.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view showing a semiconductor device using the present invention, and FIG. 2 is a plan view showing a layout of an answer-side resistor according to the present invention.

  As shown in FIG. 1, in the semiconductor device of the present invention, a silicide layer 6 is formed in a gate electrode 40 and a source / drain region 5 in order to reduce contact resistance and to form a low resistance gate, source / drain, and other electrodes. The polysilicon resistor 4 and the diffused resistor 3 are formed of unsalicide resistors.

  This semiconductor device includes, for example, a P-type well region 10 (hereinafter referred to as a P well 10) and an N type well region 11 (hereinafter referred to as an N well) on a semiconductor substrate 1 (hereinafter referred to as a substrate 1) made of P type single crystal silicon. 11) and an isolation insulating film 2 by a shallow trench isolation (STI) method is provided. In this embodiment, an N-type MOS transistor having an LDD structure is formed in the P well 10, an unsalicide diffusion resistor 3 formed of a P-type diffusion layer in the N well 11, and an unsalicide polysilicon resistor 4 on the STI isolation insulating film 2. Is provided.

  In FIG. 1, an N-type MOS transistor is described, but in the case of a P-type MOS transistor, it is formed in the same manner in an N well. Further, since the answer-side polysilicon resistor 4 may be formed on the STI isolation insulating film 2, there is no problem whether it is provided on the N well or the P well.

  In FIG. 1, a P + type polysilicon resistor 4 is provided on the N well 11. Further, an unsalicide diffusion resistor composed of an N type diffusion layer may be provided in the P well.

  In addition, a sidewall is provided on the side wall of the gate electrode 40 in order to form an N-type MOS transistor having an LDD structure. In FIG. 1, the gate insulating film is not shown.

  In order to form the silicide layer 6 on the gate electrode 40 and the source / drain region 5 by using the salicide technique after forming the N + type source / drain region 5 to be the conductive layer, the diffusion resistance 3 and the polysilicon resistance 4 is covered with a mask serving as a salicide block, and a Ti layer, for example, is deposited as a metal layer on the entire surface of the substrate 1, for example, by sputtering, and then the substrate 1 is subjected to a heat treatment such as lamp annealing. Then, the Ti layer on the silicon and the underlying silicon are reacted to form the low resistance silicide layer 6. Thereafter, the unreacted Ti layer is removed, and the silicide layer 6 is formed in a self-aligned manner only on the gate electrode 40 and the source / drain regions 5. Thereafter, although not shown, an interlayer insulating film and an electrode wiring layer are formed and subjected to a predetermined process to obtain a semiconductor device having an unsalicide resistance.

  As described above, the width of the ansalicide region is determined by the diffusion region or the polysilicon region as the lower layer, but the length direction is determined by the mask for forming the ansalicide region, and due to variations in the photographic process, The length direction is greatly different. In view of this, the present invention is designed to reduce the variation in the resistance resistance value of the high resistance, by devising the resistance element structure of the variation in the mask for forming the unsalicide region.

  As shown in FIG. 2, the answer-side resistor 3 (4) is not a simple rectangle as in the prior art, but is configured so that the width increases toward the end at the end of the answer-side resistor. The answer-side resistor 3 (4) shown in FIG. 2 is composed of a rectangular region 31 having a width of 4 μm and a length of 8 μm, and a region 32 that continues to the region 31 and increases in width toward the end. In this embodiment, the region 32 has a taper shape with an angle of 45 degrees, a length of 4 μm, and a terminal width of 12 μm. A plurality of contact regions 33 are provided in this region 32. In this embodiment, the contact region 33 is formed in a 0.36 × 0.36 μm square.

In this embodiment, the length of the answer side region when formed accurately is 12 μm. For this reason, a salicide block (SB) region 21 is provided as shown. The salicide block region 21 is formed so as to cover the distance to the region 31 and half of the region 32 connected to the region 31. That is, the rectangular region 31 and the region 32 whose width increases toward the end by 2 μm in length above and below the rectangular region 31 are the answer-side resistance regions. A silicide layer is formed in a region that is not covered with the salicide block region 21 and becomes a salicide resistor portion. Therefore, a region 2 μm from the end including the contact region 33 is a salicided salicide portion.

  The dimensions of the respective parts described above are shown as examples for confirming the effect between the resistance of the conventional structure described below and the present invention is not limited to these dimensions. It is formed with a dimension corresponding to the required resistance value.

  FIG. 3 shows a conventional unsalicide resistance having a rectangular shape with a width of 4 μm and a length of 16 μm, and a salicide block region 21 having a length of 12 μm is provided.

FIG. 4 shows a case where the salicide block region 21 is shifted by α from the desired size. When X is the desired salicide block region 21, the exposure amount is determined in a photographic process for creating a mask for forming the salicide side region. In the photographic process for creating a mask for forming the unsalicide area when the resist is shrinked or when shrinkage (shrinkage) of the resist occurs and it becomes smaller by -α, it is used for forming the unsalicide area. Table 1 and FIG. 5 show the results of simulation of how the resistance value changes when the mask becomes larger by α.

  The simulation was performed with an ansalicide polysilicon resistor, the sheet resistance of the ansalicide polysilicon resistor was 1000 Ω / sheet, and the sheet resistance of the salicide polysilicon resistor was 4 Ω / sheet. The resistance values shown in FIG. 2 when no shift occurs in the salicide block region 21 are 2667.7Ω in the unsalicide (US) region and 1.3Ω in the salicide region.

The resistance value between the contacts 33 and 33 is a value obtained by connecting the resistance of the salicide region and the resistance of the unsalicide region in series. As described above, the resistance value of the salicide resistor is larger than the resistance value of the unsalicide region. Is so small that salicide resistance is negligible. For this reason, it is possible to consider the variation state of the resistance value by comparing the resistance values of the unsalicide regions. In FIG. 5, diamonds conventional A Nsarisaido (US) resistance value of the region, a square is a resistance value of A Nsarisaido (US) region of the present invention.

  When the salicide block region 21 is displaced, the resistance value changes. As is apparent from FIG. 5 and Table 1, the resistance value of the unsalicide (US) region of the present invention changes compared to the conventional one. It can be seen that the variation of the resistance value is suppressed to less than half of the conventional value.

  Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

  First, as shown in FIG. 6, a P well 10 and an N well 11 are formed on a semiconductor substrate 1 made of P-type single crystal silicon, an isolation insulating film 2 is formed by STI, and then a gate insulating film is formed on the entire surface. (Not shown). Thereafter, a doped polysilicon film is deposited on the entire surface, a photoresist film is formed on the entire surface, and then patterned by a photolithography technique to form a photoresist pattern. Then, using the photoresist pattern as a mask, the doped polysilicon film is etched to form a gate electrode 40 serving as a conductive layer and an unsalicide resistor element 4 made of polysilicon.

  Next, after removing the photoresist film, impurities such as As or P are implanted from above the substrate 1 by an oblique rotation ion implantation method in order to form an N − -type LDD region. Next, after a TEOS film is deposited on the entire surface to a thickness of about 0.05 to 0.2 μm, the entire surface is etched back by anisotropic dry etching to form the gate electrode 40 and the side wall of the polysilicon ansalicide resistor element 4. Side walls are formed.

  Next, an impurity such as arsenic (As) or phosphorus (P) is implanted from above the substrate 1 by ion implantation in order to form the N + -type source / drain region 5 to be a conductive layer. Subsequently, in order to form the diffused resistor 3, a mask is provided, and impurities such as boron (B) are implanted from the substrate 1 side.

  In this way, an N-type MOS transistor having an LDD structure is provided in the P well 10, an unsalicide diffusion resistor 3 composed of a P-type diffusion layer in the N well 11, and an unsalicide polysilicon resistor 4 on the STI isolation insulating film 2. ing. As shown in FIG. 2, the answer-side diffused resistor 3 and the answer-side polysilicon resistor 4 are not simple rectangles, but are formed so that the width increases toward the end at the end of the answer-side resistor. Yes.

  Subsequently, a salicide technique is used to form a silicide layer on the gate electrode 40 and the source / drain region 5, and a salicide block region is formed to form the unsalicide diffusion resistor 3 and the unsalicide polysilicon resistor 4. It becomes the process to do. As shown in FIG. 7, for the salicide block, a silicon nitride (SiN) film 7 having a thickness of 20 nm to 40 nm, in this embodiment, having a thickness of 20 nm is deposited on the entire surface.

  Next, as shown in FIG. 8, a photoresist film is formed on the entire surface, and then patterned by a photolithography technique to form a photoresist pattern 8. Then, using the photoresist pattern 8 as a mask, the silicon nitride film 7 is etched to form a salicide block region 21, and the mask 8 is removed (see FIGS. 9 and 10). As shown in the plan view of FIG. 10, the salicide block region 21 is formed so as to cover a part of the portion where the width of the resistance region changes so as to cover the unsalicide diffusion resistor 3 and the unsalicide polysilicon resistor 4. The At this time, as described above, the salicide block region 21 is preferably formed in a desired size, but the shape of the unsalicide diffusion resistor 3 and the unsalicide polysilicon resistor 4 is devised even if the size slightly deviates. Therefore, variation in resistance value is suppressed.

Subsequently, as shown in FIG. 11, a Ti layer 9 having a thickness of 20 nm to 50 nm, in this embodiment, a thickness of 35 nm is deposited as a metal layer on the entire surface of the substrate 1 by, for example, sputtering. Thereafter, the substrate 1 is subjected to heat treatment such as lamp annealing, whereby the Ti layer 9 on the silicon and the underlying silicon are reacted to be transformed into a TiSi ₂ layer 6 as a low resistance silicide layer. Thereafter, the unreacted Ti layer 9 is removed using a solution such as H ₂ SO ₄ / H ₂ O ₂ . As a result, the TiSi ₂ layer 6 is formed in a self-aligned manner only on the silicon, that is, on the gate electrode 5 and the source / drain regions 10, and the high resistance unsalicide diffusion resistor 3 and unsalicide polysilicon resistor 4 are Is obtained (FIG. 13). Thereafter, an interlayer insulating film and an electrode wiring layer are formed, and predetermined processing is performed to obtain an analog circuit semiconductor device.

  The answer-side resistor 3 (4) described above is composed of a rectangular region 31 and a tapered region 32 that continues to the region 31 and increases in width toward the end. The region 32 that increases in width toward the end may be configured to increase in width in a staircase shape without being limited thereto.

It is sectional drawing which shows the semiconductor device using this invention. It is a top view which shows the layout of the answer side resistance by this invention. It is a top view which shows the layout of the conventional unsalicide diffusion resistance. It is a top view which shows the layout of the unsalicide resistance which shows the shift | offset | difference of a salicide block. It is a figure which shows the shift | offset | difference of a salicide block, and the change of resistance value. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is a top view which shows the manufacturing method of the semiconductor device based on this invention according to process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention according to process. It is a top view which shows the layout of the conventional unsalicide diffusion resistance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Separation insulating film 3 Ansalicide diffusion resistance 4 Ansalicide polysilicon resistance 5 Source / drain region 6 Silicide layer 21 Salicide block region

Claims (4)

In the semiconductor device including a resistive element that is not a semiconductor element and Salicided that are salicided, said resistive element, with a width of at least terminal portion is formed thick Kunar so towards the end comprising the contact region, the semiconductor device region to part of the portion of varying width comprising a pre SL contact region from the end portion is salicided, other parts are characterized by non-salicided.   2. The semiconductor device according to claim 1, wherein the resistance element includes a rectangular region and a region that is connected to the rectangular region so that a width of a terminal portion becomes thicker toward the terminal. .   2. The resistance element according to claim 1, comprising: a rectangular region; and a region connected to the rectangular region and formed such that a width of a terminal portion increases in a tapered shape toward the terminal. The semiconductor device described. The method of manufacturing a semiconductor device including a resistive element that is not a semiconductor element and Salicided that are salicided, forming at least resistance region width of the end portion is formed to the thickness Kunar so towards the end containing the contact areas After the salicide block region is formed including at least the contact region and a region reaching the part of the resistance region whose width changes, the salicide is formed and the salicided region is salicided. A method for manufacturing a semiconductor device, comprising forming a non-existing region.

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