JP2006108469A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method that not only prevents an area causing a high resistance silicide film from being produced on a polysilicon wire surface, but also prevents p-type impurities doped into the polysilicon wire from being diffused onto an n-type element area. <P>SOLUTION: This method consists of a process for forming an element separation film 2; a process for forming the first and second gate oxide films 4a and 4b; and a process for forming the first gate electrode 4b, second gate electrode 4a, and ploysilicon wire 4c. In addition, it comprises a process for doping n-type impurities into a polysilicon wire 4c and a first gate electrode 4b that have been positioned in a first element area 1b when viewed from the first boundary S, and a process for doping p-type impurities into a polysilicon wire 4c and second gate electrode 4a that have been positioned in a second element area 1a when viewed from the second boundary M. The first boundary S is set in the second element area 1a when viewed from the middle between the first element area 1b and the second element area 1a. The second boundary M is set in the middle of both. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention provides a semiconductor device that makes it difficult to form a region in which the silicide film has a high resistance on the surface of the polysilicon wiring, and suppresses diffusion of P-type impurities introduced into the polysilicon wiring into the N-type element region. The present invention relates to a manufacturing method and a semiconductor device.

  Each drawing in FIG. 7 is a cross-sectional view for explaining a conventional manufacturing method of a semiconductor device. First, as shown in FIG. 7A, an element isolation film 102 is formed on a silicon substrate 101 to separate a P-type element region 101a and an N-type element region 101b. Next, gate oxide films 103a and 103b are formed in the P-type element region 101a and the N-type element region 101b, respectively. Next, gate electrodes 104a and 104b are formed on the gate oxide films 103a and 103b, respectively. The gate electrodes 104 a and 104 b are connected to each other by a polysilicon wiring 104 c on the element isolation film 102.

  Then, half of the P-type element region 101a and the polysilicon wiring 104c on the P-type element region 101a side is covered with the resist pattern 110, and then N-type impurities are implanted using the resist pattern 110 as a mask. As a result, N-type impurity regions (not shown) that serve as the source and drain of the N-type transistor are formed in the N-type element region 101b. At this time, N-type impurities are also implanted into the half of the polysilicon wiring 104c on the N-type element region 101b side and the gate electrode 104b.

  Thereafter, as shown in FIG. 7B, the resist pattern 110 is removed. Next, half of the polysilicon pattern 104 on the N-type element region 101b side and the N-type element region 101b are covered with a resist pattern 112, and then a P-type impurity is implanted using the resist pattern 112 as a mask. As a result, a P-type impurity region (not shown) that becomes the source and drain of the P-type transistor is formed in the P-type element region 101a. At this time, the P-type impurity is also implanted into the half of the polysilicon wiring 104c on the P-type element region 101a side and the gate electrode 104a.

Thereafter, as shown in FIG. 7C, the resist pattern 112 is removed. Next, a metal film (for example, a titanium film or a cobalt film) is formed on the entire surface, and then heat treatment is performed. As a result, a low resistance silicide film 109 is formed on each of the gate electrodes 104a and 104b and on the polysilicon wiring 104c. Is formed. Next, the non-silicided metal film is removed.
Such a technique is described in Patent Document 1, for example.
Japanese Patent Laying-Open No. 2002-76138 (FIG. 4)

  In order for the metal film on the polysilicon wiring to be silicided, it is preferable that the polysilicon wiring contains sufficient impurities. However, when a positional shift occurs in the resist pattern when the impurity is implanted, there may be a region where the impurity is not sufficiently introduced into the polysilicon pattern, for example, as indicated by reference numeral 104d in FIG. 7B. . In this region, since the impurity concentration is low, the silicidation of the metal film becomes insufficient, and the resistance of the metal silicide film may vary.

  As a method for preventing this, it is conceivable to form an overlap region in which both N-type impurities and P-type impurities are implanted on the polysilicon wiring. At this time, if the overlap region is formed by expanding both the region where the N-type impurity is introduced and the region where the P-type impurity is introduced, the region where the P-type impurity is introduced approaches the N-type element region ( For example, refer to FIGS.

  On the other hand, boron is often used as the P-type impurity, but boron is likely to thermally diffuse in the silicide film. For this reason, when the region into which the P-type impurity is introduced in the polysilicon wiring approaches the N-type device region, boron diffuses to the N-type device region through the silicide film, which affects the characteristics of the N-type transistor. There is a possibility to give.

  The present invention has been made in consideration of the above-described circumstances, and the object thereof is to make it difficult to form a region where the silicide film has a high resistance on the surface of the polysilicon wiring, and to be introduced into the polysilicon wiring. An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing diffusion of P-type impurities into an N-type element region.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes:
Forming a device isolation film for separating the first device region and the second device region on the semiconductor substrate;
Forming first and second gate insulating films located in the first and second element regions on the semiconductor substrate;
A first gate electrode positioned on the first gate insulating film; a second gate electrode positioned on the second gate insulating film; and the first and second gate electrodes positioned on the element isolation film Forming a polysilicon wiring for connecting,
Injecting N-type impurities into the polysilicon wiring and the first gate electrode located on the first element region side from the first boundary line;
Injecting a P-type impurity into the polysilicon wiring located on the second element region side from the second boundary line and the second gate electrode;
Forming a silicide layer on each of the first gate electrode, the polysilicon wiring, and the second gate electrode;
Activating the N-type and P-type impurities by heat-treating the first gate electrode, the polysilicon wiring, and the second gate electrode;
Comprising
The first boundary line is set closer to the second element region than the middle between the first element region and the second element region, and the second boundary line is set to the middle.

  According to this semiconductor device, the first boundary line is set to the second element region side from the middle between the first element region and the second element region, and the second boundary line is set to the middle. Therefore, both an N-type impurity and a P-type impurity are introduced into a region sandwiched between the first boundary line and the second boundary line. For this reason, even if the mask is displaced in the step of implanting impurities, a region where no impurities are introduced is unlikely to occur in the polysilicon wiring. Therefore, a region where the silicide film has a high resistance is less likely to occur on the surface of the polysilicon wiring.

  The P-type impurity is introduced into a portion of the polysilicon wiring located on the second element region side from the middle between the first element region and the second element region. Therefore, the P-type impurity introduced into the polysilicon wiring is difficult to diffuse into the N-type element region.

  The distance between the first element region and the second element region may be 1200 nm or less. The distance between the first boundary line and the middle may be 200 nm or more and 500 nm or less.

  The step of implanting N-type impurities into the polysilicon wiring and the first gate electrode includes the steps of forming a photoresist film on the polysilicon wiring, the first gate electrode, and the second gate electrode, and a photoresist film. A step of exposing, and a step of forming a resist pattern having an opening on the first gate electrode and a polysilicon wiring located on the first element region side from the first boundary line by developing the photoresist film; And a step of implanting N-type impurities using the resist pattern as a mask, and the position of the first boundary line may be set by adjusting the exposure condition of the photoresist film.

A semiconductor device according to the present invention includes:
An element isolation film formed on the semiconductor substrate and separating the first element region and the second element region;
A first gate insulating film formed on the semiconductor substrate and located in the first element region;
A second gate insulating film formed on the semiconductor substrate and located in the second element region;
A first gate electrode formed on the first gate insulating film;
A second gate electrode formed on the second gate insulating film;
A polysilicon wiring formed on the device isolation film and connecting the first and second gate electrodes to each other;
A silicide film formed on each of the first and second gate electrodes and on the polysilicon wiring;
Comprising
The polysilicon wiring and the first gate located on the first element region side from the first boundary line set on the second element region side from the middle between the first element region and the second element region N-type impurities are introduced into the electrode,
P-type and N-type impurities are respectively introduced into the polysilicon wiring located between the middle and the first boundary line,
A P-type impurity is introduced into the polysilicon wiring and the second gate electrode located on the second element region side from the middle.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment. In this semiconductor device, the P-type element region 1 a and the N-type element region 1 b are separated by the element isolation film 2. A P-type transistor is formed in the P-type element region 1a, and an N-type transistor is formed in the N-type element region 1b.
The P-type transistor has a P-type gate electrode 4a and a P-type impurity region 7a serving as a source and a drain. The N-type transistor includes an N-type gate electrode 4b and an N-type impurity region 7b serving as a source and a drain. have.

  The P-type gate electrode 4a is connected to the N-type gate electrode 4b through the polysilicon wiring 4c on the element isolation film 2. The P-type gate electrode 4a, the N-type gate electrode 4b, and the polysilicon wiring 4c are integrally formed, and a silicide film is laminated on each. A side wall 5 is formed on the side wall.

  A P-type impurity is introduced into the P-type gate electrode 4a, and an N-type impurity is introduced into the N-type gate electrode 4b. In the polysilicon wiring 4c, in order from the P-type element region 1a side, a P-type region 4d into which P-type impurities are introduced, an overlap region 4f into which both P-type and N-type impurities are introduced, and N-type impurities are included. An introduced N-type region 4e is provided. The boundary S between the P-type region 4d and the overlap region 4f is set slightly on the P-type device region 1a side from the middle M between the P-type device region 1a and the N-type device region 1b. The boundary 4e is set to the middle M.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2, FIG. 3, FIG. 5 and FIG. 6, (A) is a cross-sectional view corresponding to the AA cross section of FIG. 1, and (B) is a cross sectional view corresponding to the BB cross section of FIG. (C) is sectional drawing equivalent to CC cross section of FIG. FIG. 4 is a schematic plan view for explaining a method of forming the resist pattern of FIG.

  First, as shown in each drawing of FIG. 2, an element isolation film 2 is formed on a silicon substrate 1 to separate a P-type element region 1a and an N-type element region 1b. The element isolation film 2 may be formed by a LOCOS method or may be embedded in the silicon substrate 1 by a trench isolation method. The interval between the P-type element region 1a and the N-type element region 1b is, for example, 1200 nm or less.

  Next, the silicon substrate 1 is thermally oxidized. As a result, a gate oxide film 3a located in the P-type element region 1a and a gate oxide film 3b located in the N-type element region 1b are formed on the silicon substrate 1. Next, a polysilicon film is formed on the entire surface including the element isolation film 2 and the gate oxide films 3a and 3b by a CVD method. Next, a photoresist film (not shown) is applied on the polysilicon film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the polysilicon film. Next, the polysilicon film is etched using this resist pattern as a mask. As a result, a P-type gate electrode 4a and an N-type gate electrode 4b are formed on the gate oxide films 3a and 3b, respectively. A polysilicon wiring 4 c is formed on the element isolation film 2. Thereafter, the resist pattern is removed.

  Next, the N-type element region 1b is covered with a resist pattern (not shown). Next, ions of low-concentration P-type impurities are implanted into the silicon substrate 1 using the resist pattern, the element isolation film 2, and the P-type gate electrode 4a as a mask. Thereby, a P-type low concentration impurity region (LDD) 6a is formed in the P-type element region 1a. Thereafter, the resist pattern is removed.

  Next, the P-type element region 1a is covered with a resist pattern (not shown). Next, ions of low-concentration N-type impurities are implanted into the silicon substrate 1 using the resist pattern, the element isolation film 2, and the N-type gate electrode 4b as a mask. Thus, an N-type low concentration impurity region (LDD) 6b is formed in the N-type element region 1b. Thereafter, the resist pattern is removed.

  Next, a silicon oxide film is formed on the entire surface including each of the P-type gate electrode 4a, the N-type gate electrode 4b, and the polysilicon wiring 4c by a CVD method. Next, this silicon oxide film is etched back. Thus, sidewalls 5 are formed on the sidewalls of the P-type gate electrode 4a, the N-type gate electrode 4b, and the polysilicon wiring 4c.

  Next, as shown in each drawing of FIG. 3, a photoresist film is applied on the entire surface including the P-type element region 1a and the polysilicon wiring 4c, and this photoresist film is exposed and developed. Thereby, the resist pattern 11 is formed. The resist pattern 11 covers the portion on the P-type element region 1a side of the P-type element region 1a and the polysilicon wiring 4c, but the end on the N-type element region 1b side is the P-type element region 1a. And the N-type element region 1b is located on the P-type element region 1a side by a predetermined distance from the intermediate portion. The predetermined distance here is, for example, not less than 200 nm and not more than 500 nm.

  Here, the formation method of the resist pattern 11 is demonstrated using FIG. In the present embodiment, a reticle (not shown) used for exposing the resist pattern 11 is the same as the reticle used in the prior art. Then, the opening of the resist pattern 11 is widened by adjusting the exposure conditions (for example, exposure amount and focus) of the reticle. Specifically, the opening of the resist pattern 11 is widened by increasing the exposure amount as compared with the prior art. Thereby, the end of the resist pattern 11 is located on the P-type element region 1a side by a predetermined distance from the intermediate portion between the P-type element region 1a and the N-type element region 1b.

  Note that the position of the edge of the resist pattern 11 may be set as described above by newly designing the reticle. Specifically, the value of the data bias may be adjusted so that the position of the end of the resist pattern 11 is shifted to the P-type element region 1a side by a predetermined distance from the intermediate portion. Further, in the pattern itself designed by CAD, the position of the end of the resist pattern 11 may be shifted to the P-type element region 1a side by a predetermined distance from the intermediate portion.

  Next, N-type impurities are implanted into the silicon substrate 1 using the resist pattern 11, the N-type gate electrode 4 b, the sidewall 5, and the element isolation film 2 as a mask. As a result, an N-type impurity region 7b serving as a source and a drain is formed in the N-type element region 1b.

  At this time, ions of N-type impurities are also implanted into portions of the polysilicon wiring 4c that are not covered with the resist pattern 11, and N-type regions 4e are formed in the polysilicon wiring 4c. In this state, the end of the N-type region 4e is located at the boundary S between the P-type region 4d and the overlap region 4f, that is, the P-type device region 1a a predetermined distance from the middle M between the P-type device region 1a and the N-type device region 1b. Located on the side.

  Thereafter, as shown in each drawing of FIG. 5, the resist pattern 11 is removed. Next, a photoresist film is applied on the entire surface including the N-type element region 1b and the polysilicon wiring 4c, and this photoresist film is exposed and developed. Thereby, the resist pattern 12 is formed. The resist pattern 12 covers the portion on the N-type element region 1b side of the N-type element region 1b and the polysilicon wiring 4c, but the end on the P-type element region 1a side is the P-type element region 1a. And N-type element region 1b.

  Next, a P-type impurity is implanted into the silicon substrate 1 using the resist pattern 12, the P-type gate electrode 4a, the sidewall 5, and the element isolation film 2 as a mask. As a result, a P-type impurity region 7a serving as a source and a drain is formed in the P-type element region 1a.

  At this time, ions of P-type impurities are also implanted into portions of the polysilicon wiring 4c that are not covered with the resist pattern 12. As a result, the P-type region 4d and the overlap region 4f are formed in the polysilicon wiring 4c, and the end of the N-type region 4e is located in the middle M. Since the overlap region 4f is formed, even if the resist patterns 11 and 12 are misaligned, it is difficult to form a region in which no impurity ions are implanted in the polysilicon wiring 4c.

Thereafter, as shown in each drawing of FIG. 6, the resist pattern 12 is removed. Next, a metal film (for example, a cobalt film or a titanium film) is formed on the entire surface including each of the P-type gate electrode 4a, the N-type gate electrode 4b, and the polysilicon wiring 4c by, for example, sputtering. Then, the P-type gate electrode 4a, the N-type gate electrode 4b, the polysilicon wiring 4c, and the metal film are heat-treated. As a result, a silicide film 9 is formed on each of the P-type gate electrode 4a, the N-type gate electrode 4b, and the polysilicon wiring 4c. At this time, since the impurity is implanted into the entire polysilicon wiring 4c, the silicide film 9 is easily formed in all portions on the polysilicon wiring 4c.
Next, the non-silicided metal film is removed by etching.

  Thus, according to the present embodiment, the overlap region 4f into which both the P-type impurity and the N-type impurity are introduced is formed between the P-type region 4d and the N-type region 4e of the polysilicon wiring 4c. The For this reason, it is difficult to form a region where impurities are not implanted in the polysilicon wiring 4c. Therefore, the silicide film 9 can be sufficiently formed in all parts on the polysilicon wiring 4c, and variation in resistance of the silicide film 9 can be suppressed. Such an effect becomes greater as the distance between the P-type element region 1a and the N-type element region 1b is narrower.

  The overlap region 4f is located on the P-type element region 1a side by a predetermined distance from the intermediate portion between the P-type element region 1a and the N-type element region 1b. For this reason, the distance between the region into which the P-type impurity is introduced and the N-type element region 1b is longer than in the case where the overlap region 4f is positioned on the intermediate portion. Therefore, even if boron is used as the P-type impurity, it is possible to suppress the diffusion of boron to the N-type element region 1b side through the silicide film 9.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. 2A and 2B are views for explaining a method of manufacturing the semiconductor device shown in FIG. 1, in which FIG. 1A is a cross-sectional view corresponding to the AA cross section of FIG. 1, and FIG. Sectional drawing and (C) are sectional drawings corresponded in the CC cross section of FIG. FIGS. 3A and 3B are diagrams for explaining the next step of FIG. 2, where FIG. 3A is a cross-sectional view corresponding to the AA cross section of FIG. 1, and FIG. C) is a cross-sectional view corresponding to the CC cross section of FIG. FIG. 4 is a schematic plan view for explaining a method of forming the resist pattern of FIG. 3. 4A and 4B are views for explaining a method of manufacturing the semiconductor device shown in FIG. 3, wherein FIG. 3A is a cross-sectional view corresponding to the AA cross section of FIG. 1, and FIG. Sectional drawing and (C) are sectional drawings corresponded in the CC cross section of FIG. 6A and 6B are views for explaining a method of manufacturing the semiconductor device shown in FIG. 5, where FIG. 5A is a cross-sectional view corresponding to the AA cross section of FIG. 1, and FIG. Sectional drawing and (C) are sectional drawings corresponded in the CC cross section of FIG. (A) is sectional drawing for demonstrating the conventional manufacturing method of a semiconductor device, (B) is sectional drawing for demonstrating the next process of (A), (C) is the next process of (B). Sectional drawing for demonstrating.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon substrate, 1a, 101a ... P-type element region, 1b, 101b ... N-type element region, 2, 102 ... Element isolation film, 3a, 3b, 103a, 103b ... Gate oxide film, 4a ... P-type gate Electrode, 4b ... N-type gate electrode, 4c, 104c ... polysilicon wiring, 4d ... P-type region, 4e ... N-type region, 4f ... overlap region, 5 ... side wall, 6a ... P-type low concentration impurity region, 6b ... N-type low-concentration impurity region, 7a ... P-type impurity region, 7b ... N-type impurity region, 9, 109 ... Silicide film, 11, 12, 110, 112 ... Resist pattern, 104a, 104b ... Gate electrode

Claims (6)

Forming a device isolation film for separating the first device region and the second device region on the semiconductor substrate;
Forming first and second gate insulating films located in the first and second element regions on the semiconductor substrate;
A first gate electrode positioned on the first gate insulating film; a second gate electrode positioned on the second gate insulating film; and the first and second gate electrodes positioned on the element isolation film Forming a polysilicon wiring for connecting,
Injecting N-type impurities into the polysilicon wiring and the first gate electrode located on the first element region side from the first boundary line;
Injecting a P-type impurity into the polysilicon wiring located on the second element region side from the second boundary line and the second gate electrode;
Forming a silicide layer on each of the first gate electrode, the polysilicon wiring, and the second gate electrode;
Activating the N-type and P-type impurities by heat-treating the first gate electrode, the polysilicon wiring, and the second gate electrode;
Comprising
The method for manufacturing a semiconductor device, wherein the first boundary line is set to the second element region side from the middle of the polysilicon wiring, and the second boundary line is set to the middle.   The method for manufacturing a semiconductor device according to claim 1, wherein an interval between the first element region and the second element region is 1200 nm or less. Injecting an N-type impurity into the polysilicon wiring and the first gate electrode includes:
Forming a photoresist film on the polysilicon wiring, on the first gate electrode, and on the second gate electrode;
Exposing the photoresist film;
Developing the photoresist film to form a resist pattern having an opening on the polysilicon wiring located on the first element region side from the first boundary line and on the first gate electrode; ,
Implanting N-type impurities using the resist pattern as a mask;
Comprising
The method of manufacturing a semiconductor device according to claim 1, wherein the position of the first boundary line is set by adjusting an exposure condition of the photoresist film.   The method for manufacturing a semiconductor device according to claim 1, wherein the distance between the first boundary line and the intermediate distance is not less than 200 nm and not more than 500 nm.   The method for manufacturing a semiconductor device according to claim 1, wherein the P-type impurity is boron. An element isolation film formed on the semiconductor substrate and separating the first element region and the second element region;
A first gate insulating film formed on the semiconductor substrate and located in the first element region;
A second gate insulating film formed on the semiconductor substrate and located in the second element region;
A first gate electrode formed on the first gate insulating film;
A second gate electrode formed on the second gate insulating film;
A polysilicon wiring formed on the device isolation film and connecting the first and second gate electrodes to each other;
A silicide film formed on each of the first and second gate electrodes and on the polysilicon wiring;
Comprising
The polysilicon wiring and the first gate located on the first element region side from the first boundary line set on the second element region side from the middle between the first element region and the second element region N-type impurities are introduced into the electrode,
P-type and N-type impurities are respectively introduced into the polysilicon wiring located between the middle and the first boundary line,
A semiconductor device in which a P-type impurity is introduced into the polysilicon wiring located on the second element region side from the middle and the second gate electrode.

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