KR100505416B1 - Method for fabricating semiconductor device having high resistance - Google Patents
Method for fabricating semiconductor device having high resistance Download PDFInfo
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- KR100505416B1 KR100505416B1 KR10-2003-0008268A KR20030008268A KR100505416B1 KR 100505416 B1 KR100505416 B1 KR 100505416B1 KR 20030008268 A KR20030008268 A KR 20030008268A KR 100505416 B1 KR100505416 B1 KR 100505416B1
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- Prior art keywords
- active region
- semiconductor substrate
- high resistance
- region
- isolation layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 14
- 239000001301 oxygen Substances 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 239000007943 implant Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
본 발명은 고저항을 가진 반도체소자의 제조방법을 개시한다. 개시된 발명의 방법은, 반도체기판 내에 활성영역을 한정하는 트렌치형 소자분리막을 형성하는 단계; 상기 활성영역을 포함한 소자분리막 아래의 반도체기판 부분까지 웰 영역을 형성하는 단계; 상기 반도체기판 활성영역내의 상기 소자분리막 깊이 보다 얕은 영역에 산소를 임플란트하는 단계; 및 상기 산소가 임플란트된 반도체기판의 활성영역에 벌크 산화막을 형성하는 단계;를 포함하는 것을 특징으로 한다. 본 발명에 따르면, 작은 면적에 고저항 소자 구현이 가능하여 회로 레이아웃의 축소가 가능하고, 또한, 저항소자의 디플리션을 방지할 수 있어 안정적인 고저항소자 구현이 가능하다. The present invention discloses a method of manufacturing a semiconductor device having a high resistance. The disclosed method includes forming a trench type isolation layer defining an active region in a semiconductor substrate; Forming a well region up to a portion of the semiconductor substrate under the device isolation layer including the active region; Implanting oxygen into a region shallower than the device isolation layer in the semiconductor substrate active region; And forming a bulk oxide film in an active region of the semiconductor substrate implanted with oxygen. According to the present invention, it is possible to implement a high resistance element in a small area, it is possible to reduce the circuit layout, and to prevent the depletion of the resistance element, it is possible to implement a stable high resistance element.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는, 높은 전압을 사용하는 저항소자에 적합한 고저항을 가진 반도체소자의 제조방법에 관한 것이다.종래기술에 의하면, 웰 저항을 이용하여 고저항(high resistance)을 가진 반도체소자의 구현시에는 웰 확산층의 확산 제어가 어려워 안정적인 저항층 형성이 어렵다. 또한, 종래기술에 의하면, 확산 깊이가 깊은 것으로 인해 고저항 형성에 어려움이 있다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a high resistance suitable for a resistance device using a high voltage. In the implementation of a semiconductor device having high resistance, it is difficult to control diffusion of the well diffusion layer, thus making it difficult to form a stable resistance layer. In addition, according to the prior art, it is difficult to form high resistance due to the deep diffusion depth.
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이에, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출된 것으로서, 작은 면적에 고저항 소자 구현이 가능하여 회로 레이아웃 축소가 가능하고, 저항소자의 디플리션을 방지할 수 있어서 안정적인 저항소자 구현이 가능한 고저항을 가진 반도체소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, it is possible to implement a high resistance element in a small area, the circuit layout can be reduced, it is possible to prevent the resistance of the resistance element stable resistance element It is an object of the present invention to provide a method for manufacturing a semiconductor device having high resistance that can be implemented.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 고저항을 가진 반도체소자의 제조방법은, 반도체기판 내에 활성영역을 한정하는 트렌치형 소자분리막을 형성하는 단계; 상기 활성영역을 포함한 소자분리막 아래의 반도체기판 부분까지 웰 영역을 형성하는 단계; 상기 반도체기판 활성영역내의 상기 소자분리막 깊이 보다 얕은 영역에 산소를 임플란트하는 단계; 및 상기 산소가 임플란트된 반도체기판의 활성영역에 벌크 산화막을 형성하는 단계;를 포함하는 것을 특징으로 한다. According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a high resistance, the method including: forming a trench type isolation layer defining an active region in a semiconductor substrate; Forming a well region up to a portion of the semiconductor substrate under the device isolation layer including the active region; Implanting oxygen into a region shallower than the device isolation layer in the semiconductor substrate active region; And forming a bulk oxide film in an active region of the semiconductor substrate implanted with oxygen.
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(실시예)(Example)
이하, 본 발명에 따른 고저항을 가진 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device having a high resistance according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 고저항을 가진 반도체소자의 레이아웃도이다.1 is a layout of a semiconductor device having a high resistance according to the present invention.
본 발명에 따른 고저항을 가진 반도체소자는, 도 1에 도시된 바와 같이, 일직선 방향으로, 다시말해, "I"자 형상으로 활성영역(23)이 정의되어 있고, 상기 활성영역(23)을 사이에 두고 소자분리영역(미도시)이 정의되어 있다.In the semiconductor device having a high resistance according to the present invention, as shown in FIG. 1, an active region 23 is defined in a straight direction, that is, an “I” shape, and the active region 23 is defined in FIG. Device isolation regions (not shown) are defined in between.
또한, 상기 활성영역(23)의 양 단부에는 N+ 또는 P+ 임플란트영역(20)이 정의되어 있고, 상기 활성영역(23) 전체와 양단부에 정의된 임플란트영역(20) 및 소자분리영역의 일부분에 걸쳐 N 웰 또는 P 웰 임플란트영역(27)이 정의되어 있다.In addition, N + or P + implant regions 20 are defined at both ends of the active region 23, and the implant region 20 and the portion of the isolation region defined at both ends of the active region 23 are defined. N well or P well implant region 27 is defined.
그리고, 상기 활성영역(23) 전체에 산소 임플란트영역(31)이 정의되어 있으며, 상기 활성영역(23) 양단부의 각 중앙에 n+ 또는 p+ 콘택부(33)가 정의되어 있다.In addition, an oxygen implant region 31 is defined in the entire active region 23, and an n + or p + contact portion 33 is defined at each center of both ends of the active region 23.
이와 같은 레이아웃을 가진 본 발명에 따른 고저항을 가진 반도체소자의 제조방법에 대해 설명하면 다음과 같다. Referring to the method of manufacturing a semiconductor device having a high resistance according to the present invention having such a layout as follows.
도 2a 내지 도 2d는 본 발명에 따른 고저항을 가진 반도체소자의 제조방법을 설명하기 위한 도 1의 Ⅱ-Ⅱ선에 따른 공정단면도이다.2A to 2D are cross-sectional views taken along line II-II of FIG. 1 for explaining a method of manufacturing a semiconductor device having high resistance according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체기판(21) 내에 활성영역(23)과 소자분리영역을 한정하는 트렌치형의 소자분리막(25)을 형성한 후, N형 또는 P형 불순물의 임플란트를 진행하여 상기 반도체기판(21)의 활성영역(23)을 포함한 소자분리막(25) 아래의 반도체기판 부분까지 웰 영역(27)을 형성한다.First, as shown in FIG. 2A, a trench type device isolation layer 25 defining an active region 23 and a device isolation region is formed in the semiconductor substrate 21, and then implants of N-type or P-type impurities are formed. The well region 27 is formed to a portion of the semiconductor substrate under the device isolation layer 25 including the active region 23 of the semiconductor substrate 21.
그 다음, 도 2b에 도시된 바와 같이, 트렌치형의 소자분리막(25)을 포함한 기판(21) 상에 활성영역(23)을 노출시키는 감광막패턴(29)을 형성한다. Next, as shown in FIG. 2B, a photosensitive film pattern 29 exposing the active region 23 is formed on the substrate 21 including the trench isolation device 25.
이어서, 도 2c에 도시된 바와같이, 감광막패턴을 마스크로 이용해서 저항영역으로 사용할 영역, 즉, 상기 활성영역(23) 내에 선택적으로 산소 임플란트를 실시하여 상기 활성영역(23)의 일정 깊이내에 산소 임플란트영역(31)를 형성한다. 이때, 상기 산소 임플란트영역(31)은 트렌치형 소자분리막(25)의 깊이를 넘지 않는 영역에, 즉, 상기 소자분리막(25) 깊이 보다 얕은 영역에 형성한다. 그리고나서, 상기 감광막패턴을 제거한다. Subsequently, as shown in FIG. 2C, an oxygen implant is selectively implanted into a region to be used as a resistance region, that is, the active region 23 by using a photoresist pattern as a mask, thereby providing oxygen within a predetermined depth of the active region 23. The implant region 31 is formed. In this case, the oxygen implant region 31 is formed in a region not exceeding the depth of the trench type isolation layer 25, that is, in a region shallower than the depth of the isolation layer 25. Then, the photoresist pattern is removed.
다음으로, 도 2d에 도시된 바와같이, 산소 임플란트영역이 형성된 반도체기판(21)에 대해 후속 열처리 공정을 진행하여 상기 산소 임플란트영역의 확산 반응을 통해서 상기 반도체기판(21)의 활성영역 내에 벌크 산화막(31a)을 형성한다. 이후, 도시하지는 않았으나, 공지된 일련의 후속 반도체 공정들을 진행하여 본 발명에 따른 고저항을 가진 반도체소자의 제조를 완성한다. Next, as shown in FIG. 2D, a bulk oxide film is formed in the active region of the semiconductor substrate 21 through a diffusion reaction of the oxygen implant region by performing a subsequent heat treatment process on the semiconductor substrate 21 on which the oxygen implant region is formed. It forms 31a. Thereafter, although not shown, a series of well-known subsequent semiconductor processes are performed to complete the manufacture of a semiconductor device having a high resistance according to the present invention.
상기에서 설명한 바와같이, 본 발명에 따른 고저항을 가진 반도체소자의 제조방법에 의하면, 적은 면적에 고저항 소자의 구현이 가능하므로써 회로 레이아웃도의 축소가 가능하다.As described above, according to the method of manufacturing a high resistance semiconductor device according to the present invention, the circuit layout can be reduced by implementing the high resistance device in a small area.
또한, 산소이온주입으로 실리콘기판으로부터 절연이 가능해져 저항소자의 디프리션을 방지할 수 있어 안정적인 저항소자 구현이 가능하다.In addition, since the ion can be insulated from the silicon substrate by the implantation of oxygen ions, it is possible to prevent the depreciation of the resistive element, thereby enabling a stable resistive element.
그리고, 고전압에 대한 저항소자가 접합이 전압파괴(breakdown voltage)가 높기 때문에 고전압을 사용하는 제품의 저항소자에 적합하다.In addition, since the junction of the resistor against high voltage has a high breakdown voltage, it is suitable for a resistor of a product using a high voltage.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1은 본 발명에 따른 고저항을 가진 반도체소자를 설명하기 위한 레이아웃도.1 is a layout for explaining a semiconductor device having a high resistance according to the present invention.
도 2a 내지 도 2d는 본 발명에 따른 고저항을 가진 반도체소자의 제조방법을 설명하기 위한 도 1의 Ⅱ-Ⅱ선에 따른 공정단면도.2A to 2D are cross-sectional views taken along line II-II of FIG. 1 for explaining a method of manufacturing a semiconductor device having high resistance according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 반도체기판 23 : 활성영역21 semiconductor substrate 23 active region
25 : 트렌치소자분리막 27 : 웰영역25 trench trench isolation membrane 27 well region
29 : 감광막패턴 31 : 산소임플란트영역29: photosensitive film pattern 31: oxygen implant region
31a : 벌크 산화막31a: bulk oxide film
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| KR10-2003-0008268A KR100505416B1 (en) | 2003-02-10 | 2003-02-10 | Method for fabricating semiconductor device having high resistance |
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| KR10-2003-0008268A KR100505416B1 (en) | 2003-02-10 | 2003-02-10 | Method for fabricating semiconductor device having high resistance |
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| KR20040072268A KR20040072268A (en) | 2004-08-18 |
| KR100505416B1 true KR100505416B1 (en) | 2005-08-05 |
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