JPS626657B2 - - Google Patents
Info
- Publication number
- JPS626657B2 JPS626657B2 JP5868977A JP5868977A JPS626657B2 JP S626657 B2 JPS626657 B2 JP S626657B2 JP 5868977 A JP5868977 A JP 5868977A JP 5868977 A JP5868977 A JP 5868977A JP S626657 B2 JPS626657 B2 JP S626657B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- terminal
- region
- semiconductor
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 34
- 230000006378 damage Effects 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 description 23
- 239000000758 substrate Substances 0.000 description 10
- 230000002265 prevention Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は静電破壊防止半導体素子に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device for preventing electrostatic damage.
バイポーラ型やMOS型半導体装置においては
わずかの外部からの静電圧によつてゲートおよび
PN接合部が破壊されるためにその前段に静電破
壊防止用としてシキイ値電圧が±150〜250Vとな
る素子を組込んであり、シキイ値電圧以上の電圧
が加わつたときにこの静電破壊防止素子が動作し
て被保護素子の破壊を防止している。 In bipolar and MOS semiconductor devices, the gate and
Since the PN junction is destroyed, an element with a threshold voltage of ±150 to 250V is installed in the front stage to prevent electrostatic damage, and when a voltage higher than the threshold voltage is applied, this electrostatic damage will occur. The prevention element operates to prevent destruction of the protected element.
ところで、IC（集積回路装置）に使用される
一般の半導体素子は負電圧入力時において最低−
70Vで破壊する。そこで、上記破壊防止素子を半
導体の一部に挿入することにより正、負入力に対
する破壊レベルを向上させることができるが、上
述するように従来の静電破壊素子では動作レベル
が高く、このような低入力レベルでの破壊を完全
に防止することができない。 By the way, general semiconductor elements used in ICs (integrated circuit devices) have a minimum -
Destroyed at 70V. Therefore, by inserting the above-mentioned destruction prevention element into a part of the semiconductor, it is possible to improve the destruction level against positive and negative inputs, but as mentioned above, conventional electrostatic destruction elements have a high operating level, and such Destruction at low input levels cannot be completely prevented.
本発明は上記を考慮してなされたもので、低入
力レベルでも被保護素子の破壊を確実に防止する
静電破壊防止素子を提供することにある。 The present invention has been made in consideration of the above, and it is an object of the present invention to provide an electrostatic damage prevention element that reliably prevents damage to protected elements even at low input levels.
上記目的を達成するための本発明の要旨は、第
１導電型の半導体内に形成された第１導電型とは
反対の第２導電型の第１半導体領域と、上記第１
半導体領域内に形成された第１導電型の第２半導
体領域と、上記第２半導体領域に電気的にコンタ
クトし、ボンデイングパツトにつながる端子と、
その端子から離間し、上記第１半導体領域と上記
第２半導体領域とによつて形成されたPN接合表
面にまたがつてこれら両領域にコンタクトし、か
つ被保護素子に電気的に接続する他方の端子とを
有し、上記両端子間の第２半導体領域の幅はそれ
ら端子が接しているところの第２半導体領域の幅
よりも狭く形成され、かつ上記ボンデイングパツ
ドにつながる端子のコンタクト面積は他方のコン
タクト面積よりも大きいことを特徴とする静電破
壊防止半導体素子にある。 The gist of the present invention for achieving the above object is to include a first semiconductor region of a second conductivity type opposite to the first conductivity type formed in a semiconductor of a first conductivity type;
a second semiconductor region of a first conductivity type formed within the semiconductor region; a terminal electrically contacting the second semiconductor region and connected to a bonding pad;
The other terminal is spaced apart from the terminal, straddles the PN junction surface formed by the first semiconductor region and the second semiconductor region, contacts both these regions, and is electrically connected to the protected element. the width of the second semiconductor region between the two terminals is narrower than the width of the second semiconductor region where the terminals are in contact, and the contact area of the terminal connected to the bonding pad is A semiconductor element for preventing electrostatic breakdown characterized by having a larger contact area than the other contact area.
以下、本発明を詳細に説明する。 The present invention will be explained in detail below.
第１図乃至第２図は本発明静電破壊防止素子の
一実施例である。 FIGS. 1 and 2 show an embodiment of the electrostatic breakdown prevention element of the present invention.
同図において、１はｐ型の半導体基板、２はｐ
型半導体基板１内に設けられたn+型の埋込層、
３はｐ型半導体基板１上に設けられたコレクタ領
域となるｐ型半導体基板で、エピタキシヤル成長
層から形成されている。コレクタ領域となる半導
体基板３内にはｐ型不純物拡散によりｐ型のベー
ス拡散領域４が形成されている。このベース拡散
領域４内にはｎ型不純物拡散によりｎ型のエミツ
タ拡散領域５が形成され、その領域上の一部にコ
ンタクトするようAl層からなる入力端子６が設
けられ、一方、エミツタ拡散領域５とベース拡散
領域４との接合表面上にコンタクトするようこれ
ら両領域５，４にまたがつてAl層からなる出力
端子７が設けられている。そして、このエミツタ
拡散領域４はその入・出力端子６，７間の拡散幅
Ｗが図のように端子部分の拡散幅に比べて狭くな
つている。例えば、両端子部の拡散幅が40μ〜50
μに対し、Ｗは15μになつている。上記入力端子
６には入力電圧が加えられ、出力端子７は被保護
素子に接続している。また、第１図から明らかな
ように入力端子のコンタクト面積は被保護素子に
つながる出力端子よりも大きいため電流密度が疎
となる。なお、８はｎ型半導体基板３上に形成し
たn+型の高濃度コレクタ領域でその上に電源端
子９が設けられている。図示していないが、この
電源端子９あるいは入力端子６は外部への接続を
なすためにボンデイングパツドに接続されている
ものであることはいうまでもない。 In the figure, 1 is a p-type semiconductor substrate, 2 is a p-type semiconductor substrate, and 2 is a p-type semiconductor substrate.
an n + type buried layer provided in the type semiconductor substrate 1;
3 is a p-type semiconductor substrate provided on the p-type semiconductor substrate 1 and serving as a collector region, and is formed from an epitaxial growth layer. A p-type base diffusion region 4 is formed by p-type impurity diffusion in the semiconductor substrate 3 serving as a collector region. In this base diffusion region 4, an n-type emitter diffusion region 5 is formed by diffusion of n-type impurities, and an input terminal 6 made of an Al layer is provided so as to contact a part of the region. An output terminal 7 made of an Al layer is provided across both regions 5 and 4 so as to be in contact with the junction surface between the base diffusion region 5 and the base diffusion region 4 . In this emitter diffusion region 4, the diffusion width W between the input and output terminals 6 and 7 is narrower than the diffusion width of the terminal portion, as shown in the figure. For example, the diffusion width of both terminals is 40μ to 50μ
W is 15μ compared to μ. An input voltage is applied to the input terminal 6, and the output terminal 7 is connected to the protected element. Furthermore, as is clear from FIG. 1, the contact area of the input terminal is larger than that of the output terminal connected to the protected element, so the current density becomes sparse. Note that 8 is an n + type high concentration collector region formed on the n type semiconductor substrate 3, and a power supply terminal 9 is provided thereon. Although not shown, it goes without saying that the power supply terminal 9 or the input terminal 6 is connected to a bonding pad for connection to the outside.
以上実施例で説明した構造を有する本発明によ
れば、下記の理由により上記目的が達成される。 According to the present invention having the structure described in the embodiments above, the above object is achieved for the following reasons.
入力端子６からエミツタ拡散領域５の入力側ａ
から負（正）極性高圧パルスが入力すると、エミ
ツタ拡散領域の入力側ａとエミツタ拡散領域の出
力側ｂとの間の抵抗により電圧降下が生じａより
もｂの方が高（低）電位となる。ｂとベース拡散
領域の出力端子側ｃとは共通の出力端子に接続し
ており同電位にバイアスされ、ｃとエミツタ拡散
領域の下側のベース拡散領域ｄとの間には電流が
流れないので同電位となる。コレクタ領域ｅは電
源の島であり電位としてはｅが最も高（低）く
ｄ，ａの順となる。この状態では静電破壊防止素
子はこの部分でトランジスタ動作し疑似順方向と
なり被保護素子が破壊されることはない。 From the input terminal 6 to the input side a of the emitter diffusion region 5
When a negative (positive) polarity high voltage pulse is input from , a voltage drop occurs due to the resistance between the input side a of the emitter diffusion region and the output side b of the emitter diffusion region, and b has a higher (lower) potential than a. Become. b and the output terminal side c of the base diffusion region are connected to a common output terminal and are biased to the same potential, and no current flows between c and the base diffusion region d below the emitter diffusion region. They have the same potential. The collector region e is a power supply island, and the potential of e is the highest (lowest), followed by d and a. In this state, the electrostatic damage prevention element operates as a transistor in this portion and becomes a pseudo forward direction, so that the protected element is not destroyed.
負極性パルスの入力時は、ａ，ｄ間に0.3〜
0.4Vの順方向電圧が加わると、静電破壊素子は
on状態となる。本発明のようにエミツタ拡散領
域の中央部の拡散幅を狭くなつていれば、ａとｂ
間抵抗が増大しａ，ｂ間の電位差が大となり動作
するシキイ値電圧を低下させることができ、した
がつて、低入力レベルでも被保護素子の破壊を確
実に防止することができ、被保護素子の破壊レベ
ルを向上することができる。 When inputting a negative polarity pulse, the distance between a and d should be 0.3~
When a forward voltage of 0.4V is applied, the electrostatic breakdown device will
It becomes on state. If the diffusion width at the center of the emitter diffusion region is narrowed as in the present invention, a and b
The resistance between a and b increases, and the potential difference between The level of destruction of the element can be improved.
本発明は静電破壊素子のエミツタ拡散領域の
入・出力端子間の拡散幅を狭くして両間の電位差
を大きくすればよいので、その構造は問わない。 In the present invention, the structure does not matter as long as the diffusion width between the input and output terminals of the emitter diffusion region of the electrostatic breakdown element is narrowed to increase the potential difference between the two.
本発明はバイポーラIC、MOSIC等の静電破壊
防止素子に適用できるものである。 The present invention can be applied to electrostatic breakdown prevention elements such as bipolar ICs and MOSICs.
第１図は本発明の一実施例の平面図、第２図は
そのｘ―x′視断面図である。
１…ｐ型の半導体基板、２…埋込層、３…ｎ型
半導体基板、４…ベース拡散領域、５…エミツタ
拡散領域、６…入力端子、７…出力端子、８…高
濃度コレクタ領域、９…電源端子。
FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line xx'. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Buried layer, 3... N-type semiconductor substrate, 4... Base diffusion region, 5... Emitter diffusion region, 6... Input terminal, 7... Output terminal, 8... High concentration collector region, 9...Power terminal.
Claims (1)
型とは反対の第２導電型の第１半導体領域と、上
記第１半導体領域内に形成された第１導電型の第
２半導体領域と、上記第２半導体領域に電気的に
コンタクトし、ボンデイングパツトにつながる端
子と、その端子から離間し、上記第１半導体領域
と上記第２半導体領域とによつて形成されたPN
接合表面にまたがつてこれら両領域にコンタクト
し、かつ被保護素子に電気的に接続する他方の端
子とを有し、上記両端子間の第２半導体領域の幅
はそれら端子が接しているところの第２半導体領
域の幅よりも狭く形成され、かつ上記ボンデイン
グパツドにつながる端子のコンタクト面積は他方
のコンタクト面積よりも大きいことを特徴とする
静電破壊防止半導体素子。1 A first semiconductor region of a second conductivity type opposite to the first conductivity type formed in a semiconductor of a first conductivity type, and a second semiconductor region of a first conductivity type formed in the first semiconductor region. , a terminal electrically in contact with the second semiconductor region and connected to a bonding pad, and a PN spaced apart from the terminal and formed by the first semiconductor region and the second semiconductor region.
and the other terminal that straddles the bonding surface and contacts both of these regions and electrically connects to the protected element, and the width of the second semiconductor region between the two terminals is the width of the area where the terminals are in contact with each other. A semiconductor device for preventing electrostatic discharge damage, characterized in that the contact area of the terminal formed narrower than the width of the second semiconductor region and connected to the bonding pad is larger than the other contact area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5868977A JPS53144278A (en) | 1977-05-23 | 1977-05-23 | Electrostatic destruction preventing semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5868977A JPS53144278A (en) | 1977-05-23 | 1977-05-23 | Electrostatic destruction preventing semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53144278A JPS53144278A (en) | 1978-12-15 |
| JPS626657B2 true JPS626657B2 (en) | 1987-02-12 |
Family
ID=13091507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5868977A Granted JPS53144278A (en) | 1977-05-23 | 1977-05-23 | Electrostatic destruction preventing semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53144278A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0641083Y2 (en) * | 1987-08-31 | 1994-10-26 | 松下電器産業株式会社 | Electric Yagura Kotatsu |
-
1977
- 1977-05-23 JP JP5868977A patent/JPS53144278A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0641083Y2 (en) * | 1987-08-31 | 1994-10-26 | 松下電器産業株式会社 | Electric Yagura Kotatsu |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53144278A (en) | 1978-12-15 |
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