JPS5961224A - Electronic switch - Google Patents

Abstract

PURPOSE:To prevent the generation of switching noises by switching an MOS TR gate with a main switch configuration and back gate gradually in an electronic switch having a CMOS configuration. CONSTITUTION:When the voltage of a node A of a control input terminal 6 is turned to the H level, MOS TRs 14, 15 are turned off and on respectively and a capacitor 16 is charged by a constant current source 13, so that the voltage of a node B is changed ascendingly. On the other hand, TRs 20, 21 are turned on and off respectively and a capacitor 22 is discharged by the constant current source, so that the voltage of a node C is changed descendingly. Consequently, the main switch consisting of TRs 1, 2 is turned from off to on gradually. If the voltage of the node B drops down to 0, node voltages D, E are changed and the node F of the back gate of the TR1 is switched from the node B side to the input terminal 4 side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a CMO5IC with improved switching noise.
This relates to a 114-built electronic switch.

Conventional configurations and their problems In recent years, audio equipment, etc., use signal switching means.
Electronic switches have come to be used more often than mechanical switches because they have a superior operating feel, offer greater flexibility in design placement, and are easier to control using microcomputers.

Among them, 0 which combines P channel/l/Mos+- transistor and N channel/l/MO8) transistor
Those with MO8 structure have become mainstream.

FIG. 1 shows a typical circuit example of a conventional 0MO8 structure electronic switch.

In FIG. 1, 1 and 2 are N-channel and P-channel MOS transistors constituting the main switch, 3 is an inverter, 4 and 5 are input and output terminals of the main switch, respectively, 6 is a control input terminal, and 7 and 8 are N-channel MOs and P-channel MOs, respectively, which constitute a switch for connecting and disconnecting between the seven large gates of the switch 1 and the input terminal 4 of the main switch.
3 is an N-channel MOS l-transistor, and 9 is an N-channel MOS l-transistor that constitutes a switch for connecting and disconnecting between the back gate and the negative power supply.

The operation of the electronic switch shown in FIG. 1 will be explained.

First, when the control mansaw terminal 6 is at high level, the N channel) vMO51-Run Star 1 and P channel/L/MO
Both S transistors 2 are conductive and the main switch is conductive. At this time, the MOS) range nut 7.8 becomes conductive, and the MOS l range nut 9 becomes open CM, so that the back gate of the MO8I range nut 1 is connected to the input J terminal 4 of the main switch.

Next, when the control input terminal 6 becomes a low level, the main switch becomes open, and the terminal 1 of the MO8I-range nut 1 is still connected to the negative power supply.

As mentioned above, when the main switch is conductive, the MOS)
Connect the back gate of Langinuta 1 to input terminal 4 of the main switch.
This is to prevent distortion from occurring in the nonlinear capacitance component due to the depletion layer between the source, drain, and gate of MOS transistor 1 and the gate, and the main switch is still open. MOS at the time of
) Connecting the back gate of Rangemetal 10 to the negative power supply is necessary to fully open the MOS transistor 1.

By the way, in the conventional electronic switch as shown in Fig. 1, when switching the switch, both M
Through the capacitance between the gates and channels of O8+/Langinuta 1 and 2, and between the hack gate and channel of N-channel MO3I/Lanshinuta, the gate and Basokuge-1-
There was a problem in that sudden voltage changes leaked toward the channel, causing switching noise.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide an electronic switch having a 0MO8 structure that does not generate switching noise when switching the switch.

Structure of the Invention The electronic switch of 0MO8 configuration according to the present invention has a gate of an N-channel 7yMO3) range nut and a P-channel MO8.
8) The gate of the MOS transistor is changed with a gentle slope, and the back gate of the MOS transistor is changed with a gentle slope between the power supply and the main switch input terminal, and the back gate is changed with a gentle slope. By switching at the zero-crossing point of the voltage, switching noise is prevented from occurring.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows an embodiment of the present invention. In Figure 2,
1 to 9 correspond to the same numbers in Figure 1, and 10
are N-channel MO3) P-channel MOS transistors 11 to 16 that constitute a switch together with the range nut 9.
17 to 22 are inverters, constant current sources, current switch N-channel and P-channel MO3) transistors and capacitors, which constitute slope signal generation means, 23 is a comparator, 24 is an inverter, 25 is a resistor, and 26 is a positive side Power supply terminal, 27 is negative power supply terminal, 28.2
9 are terminals for connecting capacitors 16 and 22, respectively, and 3o
3 is a ground terminal, and 31 is an IC of 0MO8 structure constituting an electronic switch including 1 to 3 degrees. Moreover, in FIG. 2, A-F indicates each node of the circuit.

The operation of the electronic switch of this embodiment configured as described above will be explained with reference to the voltage waveforms at each node shown in FIG. In addition, in FIG. 3, a to fld are voltage waveforms of each of NOFA to F in FIG. 2, VDD is a positive power supply voltage, and Vss is a negative power supply voltage.

First, the voltage at the control input terminal 6, that is, the node A is
As shown in a, when the low level /L/ (hereinafter abbreviated as "H") changes from low level /L/ (hereinafter abbreviated as "H") to high level /I/ (hereinafter abbreviated as H), the Mo8 l-range meta 14 is turned OFF.

15 is turned on and the capacitor 16 is charged by the constant current source 13, so the voltage at node B changes in an upward slope as shown in FIG. OFF and capacitor 22
is discharged by the constant current source 18, so the node C is
As shown in Figure C, it changes with a downward slope.

At this voltage of nodes B and C, Mo8) Ranjimetal 1.20
Since it is driving game 1-, Mo8) range meta 1,
The main switch made by 114 in 2 gradually turns from OFF to ON.
It will change to.

Then, the voltage at node B changes to the ground voltage (O
v), the voltage at the output point J of the comparator 23, that is, the voltage at the node D changes from L to H as shown in FIG. 3d, and the voltage at the node E changes from H to H as shown in FIG. 3e. Changes to L. Since the voltages at nodes D and H drive the Mo5t-range metals 7, 8, 9, and 10 that constitute the switch, the Mo8) range metal 10 bank gate node F is switched from the node B side to the input terminal 4 side. .

As a result, the voltage at node F has a waveform as shown in FIG. 3f. (B, L, waveform f in FIG. 3 shows the case where the voltage at the input terminal 4 is at the ground level.

After time t2, the voltages at nodes B and O continue to change and reach VDD and vSS, respectively, and the main switch is completely turned on.

Next, when the voltage at node A changes from H to L at time t6, node F gradually switches from the input terminal 4 side to the node B side at time t4, in an operation opposite to that described above. As it changes towards Vss, the main switch also gradually turns on.
It changes from to OFF.

As described above, according to this embodiment, the Goo1 voltage of Mo8) range metals 1 and 2 constituting the main switch is gradually changed, and the back gate voltage of Mo8) range metal 1 is also gradually changed. Therefore, switching noise is not generated through capacitances between gates, channels, and back gates and channels during switching.

In addition, if Mo5) the backgate 1- of the range meter 1 is switched at a point where the voltage at node B and the voltage at the input terminal 4 are not equal, the voltage at the backgate 1- will change rapidly by the voltage difference at the time of switching. This appears as switching noise via the capacitance between the back gate and the channel, but in this embodiment, at least when the signal level of the input terminal 4 is very low (that is, almost the ground potential),
Since the back gate is designed to switch when node B and input terminal 4 are at the same potential, switching noise does not occur.

By the way, when such an electronic switch is used to switch audio signals, switching noise is not so noticeable when the signal level is high, but becomes very noticeable when the signal level is low or when there is no signal. Therefore, this embodiment is effective because the switching noise is reduced especially when the signal level is low. If the switching is performed when the signal level is still high, for example, the voltage at the input terminal 4 will change from t1 to t2, or from t6 to t4 in Figure 3.
1. In other words, the voltage at node F may become lower than that. At that time, the source of MOS transistor 1 (
Since a forward bias is created between the back gate (or the drain) and the back gate, and a forward current flows, there is a risk of a latch-up phenomenon occurring in the ayos structure. Therefore, in this embodiment shown in FIG. 2, the forward current value is limited by inserting a resistor 26 to prevent it from reaching the latch-up region. Note that the same effect can be obtained even if the resistor 26 is inserted between the back gate of the MOS transistor 1 and the switch 9°10.

Note that the slope signal generating means 1 in the embodiment shown in FIG.
1 to 16 and 17 to 22, the constant current sources 12 and 18 and 13 and 19 may be used in common as shown in FIG. 4, or the constant current sources 12 and 13 may be used in common as shown in FIG.
, 18, 19 and MO8 for current switch) Langinuk 14
, 15, 20° 21 may be exchanged.

In addition, since the main input terminal MC) S) terminals 1 and 2 are usually large in area, their gate capacitance is quite large. Therefore, this capacitance R (is the capacitor 16
, 22 can also be used. By the way, if there is an offset in the signal applied to the input terminal 4, if there is an offset in the comparator 23, or if there is a time delay in subsequent circuits including the comparator 23, the back gate is connected to the node B and the input terminal 4. When switching between the two voltages, the voltages on both sides are not necessarily at exactly the same potential. Therefore,
If there is a period in which switches 7, 8 and switch 9°1o are ON at the same time, at that time, input terminal 4 and node B are momentarily connected, and therefore the voltage at input terminal 4 is pulled by the voltage at node B. This may cause switching noise.

Therefore, it is necessary to drive the switch 7.8 and the switches 9 and 10 so that they are not turned on at the same time.

FIG. 6 shows an example of a drive circuit that drives the switch 7.8 and the switches 9 and 10 so that they are not turned on at the same time. In FIG. 6, 32 to 35 are inverters, 36 is a NAND gate, 38 is a NOR gate, 37.39 is an inverter, ■ is an output node of inverter 35, and 07 to G
10 is a node connected to the MOS transistors 7 to 100 gates, respectively.

FIG. 7 shows the voltage waveforms d and i at node D in FIG. 6, the outputs of inverters 32 to 34, node E, and nodes 0 to G10.
+~ix, i, g+~g10 and switch states are shown. In h of FIG. 7, hl indicates the ON period of the switches 9 and 10, and h2 indicates the ON period of the switch 7.8.

As can be seen from FIG. 7, if the drive circuit shown in FIG.
Since it never becomes N, switching noise due to offset etc. can also be prevented.

In the embodiment shown in FIG. 2, N-channel/I/MOS
I am trying to switch back game 1- of transistor 1, but depending on the 0MO8 structure, P channel MO3
) There is also a case where the passwords 1 to 1 of transistor 2 are switched, and the present invention is also effective in that case.

Effects of the Invention The present invention gently changes the gate and gate of the input terminal constituting the main input terminal, and furthermore, changes the gate of the input terminal at the point where the slope signal and the input signal are at the same potential. By switching, noise at the time of switching can be eliminated. Furthermore, by providing a gap between the back gate of the MOS transistor and the switch means or the switch means, latch-up can be prevented. Furthermore, switching noise caused by offset can also be prevented by preventing simultaneous ON periods from occurring in the switches that change the bank gates (that is, allowing them to perform disconnection and subsequent connection operations).

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional electronic switch, FIG. 2 is a circuit diagram of an electronic switch according to an embodiment of the present invention, FIG. 3 is an operating waveform diagram of the embodiment of FIG. 2, and FIGS. FIG. 6 is a circuit diagram of another embodiment of the slope signal generating section constituting the present invention.
The figure is a circuit diagram of another embodiment of the driving section of the switch means constituting the present invention, and FIG. 7 is an operation waveform diagram of the embodiment of FIG. 6. 1.2... Complementary MOS transinuta, 6.
... Control input terminal, 7-10... Switch means, 11-16. 17-22 River...
Slope signal generating means, 23... Comparator, 26
······resistance. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 64 Figure 3 Figure 4 Figure 5

Claims (5)

[Claims] (1) A slope signal generating means for generating two slope and downward slope signals according to a human control signal; Complementary MoS transistors connected in parallel to each other, a comparator for comparing the slope signal with the basic voltage, and the M O
An electronic null shift means for switching the back gate of the S + - range null between the source or drain of the MO3+ run transistor and the output of the slope signal generating means according to the output signal of the comparator. (2) Slope signal generating means is connected between a capacitor, the capacitor and a positive power source, and between the capacitor and a negative power source, and includes first and second signals connected intermittently in an opposite phase relationship to each other. 2. The electronic switch according to claim 1, further comprising a current source. (3) The electronic switch according to claim 2, wherein the capacitor is a gate capacitance of a Mo8 transistor whose gate is driven by a slope signal. (4) Mo8) The electronic nut cell according to claim 1, characterized in that it has a back gate and a cell nut. (5) The electronic Nuisochi according to Claim 1, wherein the Nuinochi means performs an intermittent and rearward engagement operation.