JPS5961162A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the semiconductor integrated circuit, in which relative accuracy among circuit elements in an IC chip is excellent even when the circuit is enclosed in a package, by arranging each of element pairs requiring relative accuracy among the elements at symmetrical positions to the central point or the central axis of the semiconductor chip. CONSTITUTION:The circuit elements 12a, 12b are arranged at the positions as point symmetries to the central point 14 of the IC chip 10. Consequently, the circuit is enclosed in the package, and stress applied to both elements 12a, 12b is approximately equalized mutually. Accordingly, the quantities of change of element values are also equalized mutually, thus maintaining the relative accuracy of both elements at a high value. It is preferable that not only the positions but also shapes and the directions of extensions are symmetrized mutually in these element pairs 12a and 12b.

Description

[Detailed description of the invention]

(1) Departure

TECHNICAL FIELD OF THE INVENTION The present invention relates to analog semiconductor integrated circuits. (2) Background of the Technology An A/D/A converter with a height of 1h11 degrees requires extremely high relative precision between some of its circuit elements. For example, in a D/A converter, the resistance value of the reference current generation resistor and the resistance value of the output current/voltage conversion feedback resistor are required to be equal to each other with very high precision, or the ratio of the two must be constant. . When attempting to construct this type of device using semiconductor integrated circuits (semiconductor ICs), recent advances in mask technology and process technology have enabled the relative precision between circuit elements to be increased to a considerable degree. Therefore, a high-precision IC chip can be formed. (3) Conventional technology and problems However, the above-mentioned high precision can only be achieved in the case of a single chip, and when this type of IC chip is packaged, slight changes in the characteristics of the circuit elements occur. I bite. That is, pancaging generally involves attaching an IC chip to a metal substrate provided on a ceramic plate using various adhesives such as gold silicon (AuSi), gold (Au),
gold paste. However, since there is a large difference in the coefficient of thermal expansion between this metal substrate and the IC chip, when the package temperature changes, stress is applied to the chip, which causes the element values within the chip to change. It changes and changes. (4) Purpose of the present invention Therefore, the present invention solves the above-mentioned problems of the prior art, and the purpose of the present invention is to
An object of the present invention is to provide a semiconductor integrated circuit in which relative accuracy between circuit elements within a chip is prevented from deteriorating. (5) Structure of the Invention A feature of the present invention that achieves the above-mentioned object is that each element pair, which is an element formed in a semiconductor chip and requires relative precision between elements, is positioned at the center point of the chip or This is because they are placed in symmetrical positions with respect to the central axis. (6) Embodiments of the invention The present invention will be described in detail below with reference to the drawings. FIG. 1 represents one embodiment of the invention. In the figure, 10 is an IC chip, 12a and 1
2b is a circuit element (resistance element) formed within the IC chip 10, which requires high relative accuracy. These circuit elements 12a and 12b are arranged at positions symmetrical with respect to the center point 14 of the IC chip 10. Accordingly, after being sealed in a package, the pixel elements 12a, 1
The stresses applied to the pixels 2b are approximately equal to each other, and therefore the amounts of change in element values are also equal to each other, so that the relative accuracy of the pixel elements is maintained at a high value. Note that it is desirable that these element pairs 12a and 12b are symmetrical not only in position but also in shape and direction of extension. FIG. 2 represents another embodiment of the invention. In this example, the circuit elements 16a and 16b are IC chips]
8 is provided at a line symmetrical position with respect to the longitudinal center line 20 of the frame 8. The effects of this embodiment are the same as those of the embodiment shown in FIG. It is desirable that the element pairs 16a and 16b are symmetrical not only in their positions but also in their shapes and extending directions. FIG. 3 shows yet another embodiment of the invention. In this example, the circuit elements 22a and 22b are provided at positions symmetrical to the horizontal center axis 26 of the IC chip 24. This embodiment is identical to the embodiment of FIG. 2, except that the centerline is in the transverse direction. Although the three embodiments have been described above, it is desirable that these pairs of circuit elements be placed as close to the outer periphery of the IC chip as possible. That is, as shown in FIGS. 4(A) and 4(B), the rate of change in resistance of each resistive element 30 with respect to the stress applied to the IC chip 28 increases as the resistance element 30 is located in the center of the IC chip 28. It is. In addition, the fourth
Figure (A) shows the rate of resistance variation when a constant mental force is applied to the IC chip for the resistance element 30 patterned on the IC chip 28 as shown in Figure 4 (B). It is. FIGS. 5 and 6 show still other embodiments of the present invention, in which the pattern shape of the circuit element requiring high relative accuracy is somewhat complicated. The embodiment shown in FIG. 5 is a case of a resistor element, and the IC chip 3
Each resistor element 34a, 34b formed on 2. 34 c and 35 d are the center point 36 of the IC chip 32
The positions, shapes, and extension directions are point-symmetrical to each other. The embodiment shown in FIG. 6 is a case of a transistor, and each transistor element 40a, 40b, 40c, 40d formed on an IC chip 38 is connected to a chip center point 40.
They are provided point-symmetrically with respect to each other in terms of position, shape, and direction of extension. Note that in the transistor element 40a, E
indicates the emitter, B indicates the pace, and C indicates the collector. (7) Effects of the Invention As explained in detail above, according to the present invention, each of the element pairs is arranged at a symmetrical position with respect to the center point or central axis of the IC chip. However, the relative accuracy between these elements does not deteriorate significantly even if stress due to thermal expansion is applied to the IC chip, so a semiconductor integrated circuit with good relative accuracy between elements can be realized.

[Brief explanation of drawings]

Figures 1, 2, 1 and 3 are pattern diagrams of an embodiment of the present invention, Figures 4 (A) and CB) are diagrams explaining the relationship between circuit element orientation and resistance fluctuation rate, 5th R1. Figures 6 and 1 are pattern diagrams of other embodiments of the present invention. 10.18,24,28,32.38...IC chip, 12a, ]2b, 16a, 16b, 22a,
22b, 32a, 32b. 32c, 32d, 40a, 40b, 40c,
40d,,, GB2 child, 14.36.42...center point, 20.26...center axis. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akira Yamaguchi Figure 4

Claims (1)

[Claims] 1. Each element pair that is formed in a semiconductor chip and requires relative precision between the elements is arranged at a symmetrical position with respect to the center point or central axis of the chip. A semiconductor integrated circuit characterized by: 2. The semiconductor integrated circuit according to claim 1, wherein the extending directions of the pair of elements are made symmetrical to each other. 3. The semiconductor integrated circuit according to claim 1, wherein the element pair is arranged near the outer periphery of the chip.