JPS595933B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and in particular, a device for receiving information from a ground signal such as an automatic train stop device of railway vehicle operation safety equipment on a train and making a logical judgment on the information. The present invention relates to an information processing device suitable for use in the present invention.

Conventionally, in the aforementioned automatic train stopping devices, etc., the amount of information to be transmitted from wayside signals increases as the vehicle operating speed increases, and in order to cope with this increase in information, various frequencies are used. Measures have been taken to express one piece of information by a combination of .

However, this naturally means that the logical judgment processing in the equipment mounted on the vehicle tower becomes more complicated. Conventionally, this logical judgment processing is performed using a relay logic circuit, so the logical judgment processing This requires a huge number of contacts, resulting in an increase in the size of the device.

On the other hand, as the number of contacts increases, the reliability of the device also decreases, and relay logic circuits also have the drawbacks of delayed response in the event of an abnormality, and the drawbacks that it is extremely difficult to configure a circuit based on fail-safe logic.

Therefore, the present invention was devised in view of the above-mentioned shortcomings of the prior art, and its purpose is to quickly process logical judgments of various information using a small circuit configuration, and to always operate safely in the event of an abnormality. An object of the present invention is to provide an information processing device that performs the following operations.

In order to achieve such an object, the information processing device according to the present invention uses an integrated circuit to carry out the necessary logical judgment processing, thereby reducing the size of the device and speeding up the processing. The logic circuit has a circuit configuration that ensures consistent fail-safety.

Hereinafter, this invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 1 is an inverter that inverts input information A having an arbitrary m-bit (m≧1) configuration, and 2 is an inverter that inverts input information A with n bits (m≧1).
An information conversion coater 3 converts the input information A given from the inverter 1 into the first information A'' having a bit (n>2) configuration, and converts it into the second information A'' having an n bit (n>2) configuration. A coater for information conversion, the coaters 2 and 3
The first information and the second information outputted from each of the above are combination information expressed by a combination of r bits (2≦r<n) among n bits.

Therefore, the coaters 2 and 3 output the first information A'' and the second information A'', which are n-bit combination information that is complementary to each other. 4 and 5 are registers that temporarily store the first information N and second information N, respectively; 6 is an exclusive OR of the first information N output from register 4 and the second information N output from register 5; 7 is a clock oscillator that generates clock pulses φ1 and φ2 of a predetermined period set in a mutually complementary time relationship; 8 is a register 4; 9 is a gate through which the first information N outputted from the clock pulse φ2 is passed through at the timing of the clock pulse φ2, 9 is a gate through which the output information EX from the exclusive OR circuit 6 is passed at the timing of the clock pulse φ1, and 10 is the output information A of the gate 8. '' and an OR gate that transfers the output information EX of the gate 9 to the register 11 and stores it; 11 is the output information A'' or E from the OR gate 10;
A register 12 temporarily stores X, and 12 is a drive circuit that converts each bit output of n-bit output information outputted from the register 11 into DC to drive n relays R1 to Rn. As shown in a concrete example, the input signal Q
After being amplified by an amplifier 120, the signal is led to a rectifier circuit 122 via a transformer 121 to convert it into a DC signal, and a circuit that drives a relay R using this DC signal corresponds to each of the relays R1 to Rn to be driven. It is provided.

The meaning of converting each bit output of the register 11 into DC will be described later. 13 is a decoding circuit using contacts of relays R1 to Rn that decodes information held in relays R1 to Rn, and each output signal 0U1 to 0Un of this decoding circuit 13 is used as output information for input information A, for example, in a speed checker. etc. will be supplied.

In such a configuration, for convenience of explanation, input information A is assumed to have a 1-bit configuration, and first information N and second information A' output from coaters 2 and 3 are expressed as a combination of 2 bits out of 6 bits. The operation will be explained assuming that this is the combination information.

First, when input information A becomes "1", coaters 2 and 3
outputs a combination of first information A'' and second information N that are complementary to each other, as shown in Table 1 below, for example.

Exclusive OR processing is performed for each bit of the first information A'' and the second information A in the exclusive OR circuit 6.

As a result, the exclusive OR circuit 6 outputs output information EX as shown in Table 2 below. The information EX thus obtained passes through the gate 9 at the timing of the generation of the clock pulse φ1, and is further supplied to the register 11 via the OR gate 10.

On the other hand, the first information N temporarily stored in the register 4 passes through the gate 8 at the timing of the generation of the clock pulse φ2 and is supplied to the register 11 via the OR gate 10.

Therefore, the information EX and the first information A'' are alternately input to the register 11 in accordance with the clock pulses φ1 and φ2, and from this shift register 11, 2 bits out of 6 bits are alternately input into binary values. The level 1 bit and "O" are repeated, and the information that the other bits are always at the "4 bit level" is obtained.

FIG. 4 is a time chart showing clock pulses φ1, φ2, input information of the shift register 11, and outputs of each bit B6 to B1. Therefore, like this 6
When information is supplied to the drive circuit 12 in which bits B6 and B5 alternately repeat binary levels, this bit B
Only relays R6 and R5 corresponding to relays R6 and B5, respectively, are driven. Then, the decoder 13 outputs an output signal 0Un corresponding to the combination of bits B6 and B5.
As is clear from the above description, the information processing device in this embodiment first creates first information and second information as combination information that is complementary to each other based on input information,
Next, create third information (corresponding to information EX) by exclusive ORing the first information and the second information, and supply this third information and the first information to the register in a complementary time relationship. As a result, among the combinational information consisting of n bits, only the meaningful bits as a combination of bits are obtained that change in alternating current, and this is converted to direct current and then decoded to obtain output information corresponding to input information. This is what I did. Therefore, in FIG. 1, when the complementary relationship between the first information N and the second information N output from the first coaters 2 and 3 no longer holds true, which of the two clock pulses φ1 and φ2 will be generated? When the bits run out, the register 11 cannot provide information on the combination of meaningful bits changing in an alternating current manner.In this case, the decoding logic of the decoder 13 can be used to output, for example, a train stop signal. Operation can always be ensured on the safe side.

Furthermore, if the exclusive OR processing of the exclusive OR circuit 6 is not executed correctly, the shift register 11 outputs combination information that changes AC in addition to r bits, which are meaningful as a combination of bits. Therefore, in this case as well, the safety side can always be ensured by the decoding logic of the decoder 13, as in the case described above.

Therefore, the first information A'' and the second information N are combined information,
In other words, a redundant code structure with extra bits added compared to the number of bits required to obtain the specified output information is used.
Furthermore, the meaning of creating the information EX by exclusive OR processing of the first information A'' and the second information A'' in this redundant covado configuration is that the remaining bits other than r bits, which are meaningful as a combination of bits, are always DC current. Therefore, with the above configuration, output information can be quickly output in response to input information, and in the event of an abnormality, the safety side is always maintained. operation can be ensured.

Note that in this embodiment, registers 4, 5, and 11 are not required if the input information A is provided from an external register or the like. Furthermore, the drive circuit 12 and the decoder 13 may be constructed of integrated circuits or the like other than those illustrated in FIG. FIG. 5 is a circuit diagram showing another embodiment of the present invention, and is a two-series version of the configuration shown in FIG. 1, and the same parts as in FIG. 1 are represented by the same symbols. There is.

In this case, the clock oscillator 7 generates four-phase clock signals φ1 to φ1 as shown in the time charts shown in FIGS.
φ4, and the clock signal φ, is output from the gate 9 of the first series.
Furthermore, the clock signal φ2 is supplied to the gates 8 of the first series, the clock signal φ3 is supplied to the gates 9 of the second series, and the clock signal φ4 is supplied to the gates 8 of the second series. . Therefore, in such a configuration,
The output information of the gates 8 and 9 of the first series are represented by A′1 and EXl, respectively, and the output information of the gates 8 and 9 of the second series are represented by A″2 and EX2, respectively.
Expressed as follows, the shift register 11 first has information EXl
But then information A'1, then information EX2, then information A
'2 are input in a mutually complementary time relationship, and at this time, if the first information A'' and N are as shown in Table 1 above, each bit B6 of the shift register 11
- B1 outputs combination information similar to the embodiment of FIG. 1, as shown in FIG. 6 fk.

In this way, by arranging the configuration of FIG. 1 into two series, one series can perform the function of constantly monitoring the processing of the other series, and the fail-safe logic function can be improved compared to the embodiment of FIG. 1. It has the advantage of being able to use soil.

FIG. 7 is a block diagram showing an embodiment in which the information processing device according to the present invention is applied to a point information detection device in an automatic train stopping device. In the figure, 0S is a constant frequency F when there is no electromagnetic coupling with the ground equipment.

When electromagnetic coupling is made between the resonant coil WC of the ground device and the pick-up coil PC, the oscillation frequency f1 is selected by the frequency switching contacts r1 to Rn.
~Oscillation amplifier circuit that immediately transitions to Fn, SAO~SAn
is a selective amplifier circuit which uses the oscillation output of the oscillation amplifier circuit 0S as a common input, and these selective amplifier circuits SAO-SA
n is an oscillation frequency F assigned to itself in advance. A predetermined output signal is output only when -Fn is given. For example, the selective amplifier circuit SAO has an oscillation frequency F. outputs a predetermined output signal only when
After being rectified through a rectifier REC, it is supplied to the main relay MR, thereby driving the main relay MR. Further, the selective amplifier circuit SAl outputs an output signal a of "1" only when the oscillation frequency f1 is given.Selective amplifier circuits SA2, SA3......SAn also oscillate. Output signals B, c of ゜“1”゜ only when frequencies F2, f3......Fn are respectively given.
・・・・・・・・・Outputs k. 0SC is the previous 6th
A four-phase clock signal φ similar to that shown in Figures a-d.
Clock oscillators HDl to HDn, which output signals 1 to φ4, hold output signals A, b, . The related output signal A,i. b, I...
...K, k, hold circuits CDl and CD2 output signals A, a. b, b, ...... First information A, B as combination information that is mutually complementary based on K, k.
...゜゜...K and second information A, B...
・A first series coater section and a second series coater section that respectively output K, and these are input signals A, i, b, '
b...Coaters CDa, CDSL, CDb, CDi corresponding to K, ``k, respectively)...
...Equipped with CD'k.

Note that the first series coater section CDl and the second series coater section CD2 operate only when the main relay MR is falling, that is, due to electromagnetic coupling between the resonance coil WC of the soil device and the pick-up coil PC of the on-board device. Therefore, the oscillation frequency F of the oscillation amplifier circuit 0S. It operates only when the oscillation frequency shifts to other different oscillation frequencies f1 to Fn. LG, to LG2 are the corresponding first series coater unit CDl and second series coater unit C, respectively.
First information A, B given from D2...
K1 A first series logic unit and a second series logic unit that perform the same processing as in the case of FIG. 1 above based on second information A, B...K, Logic section LG1 is supplied with clock signals .phi.1 and .phi.2, and second series logic section LG2 is supplied with clock signals .phi.3 and .phi.4.

By the way, in this case, the first series logic unit LGl and the second
As shown in the detailed block diagram of FIG. 8, the series logic unit LG2 receives input first information A, B, etc. in order to perform a specific function as a point information detection device.
・K and second information X, l...The code comparison unit CMP for determining whether K has a valid code structure and the input information correspond to items that should be determined independently. It is provided with a determination unit JD that determines whether the input information corresponds to composite information that should be determined in combination with other input information.

Coat male? When the section CMP is instructed by the discriminating section JD that the input information should be judged independently, the section CMP compares the input information with the corresponding comparison information, and also determines whether the input information is a combination of several input information. If it is instructed that something is to be determined, it waits for some input information to be provided and then compares these input information with the corresponding comparison information. When the input information is determined to be valid, the input information is transferred to registers RGl and RG2.
Output to. However, in the case of composite information that is judged based on a combination of several pieces of input information, new information is created in place of the input information at this time, and this is output to registers RGl and RG2. In this case, the comparison information N-K' corresponding to the first information A-K is stored in advance in the memory M1, and the comparison process is executed by the comparator CMPl. Also, the second
Comparison information N corresponding to information A to K;? It is stored in advance in the memory M2, and the comparison process is executed by the comparator CMP2. The subsequent processing is performed in the same manner as in the case of FIG.

That is, exclusive OR processing is performed on the first information and second information temporarily stored in registers RGl and RG2, respectively, by exclusive OR circuit EXG. and,
Information EX representing the exclusive OR processing result passes through gate AG2 and OR gate 0G1 at the timing of the generation of clock pulse φ1 (φ3 in the second series logic section), and further passes through OR gate 0G2 in FIG. ~ On the other hand, the first information temporarily stored in the register RGl passes through the gate AGl and the OR gate 0G1 at the timing of the generation of the clock pulse φ2 (φ4 in the second series logic section), and further passes through the OR gate 0G2 in FIG. It passes through and is supplied to register RG3.

Therefore, in the register RG3 of FIG. 7, r bits out of n bits alternately repeat binary levels, and the remaining bits are always "15", as in the embodiment described in FIG.
The combination information that has become a "level" is stored.Then, the output information of this register RG3 is converted into direct current in the drive circuit DRV and is supplied to the relays R1 to Rn.Thereby, the binary level is repeated. Only the relay corresponding to the bit operates, and the information resulting from the relay operation is decoded by the decoder DEC.Then, the decoded outputs 0U1 to 0Un of this decoder DEC are supplied to, for example, a speed checker.The speed checker is When receiving any of the Q decode J outputs 0U1 to 0Un from the decoder DEC, a reply signal AN is sent back to the point information detection device.

As a result, the relay RER operates, and the first series logic section L
Gl and the second series logic unit LG2 are reset and initialized. In Fig. 7, relay MPR is an auxiliary relay that performs an auxiliary function of main relay MR, and the contact points of this auxiliary relay MPR correspond to the time width when sending decoded outputs 0U1 to 0Un of decoder DEC to the speed checker. is used to control.

In the point information detection device configured as described above, the oscillation amplification circuit OS has a constant frequency F when there is no electromagnetic coupling with the resonant coil Wc of the ground equipment. The main relay MR is driven by this, but when the pick-up coil PC and the resonance coil WC are electromagnetically coupled, the frequency switching contacts r1 to Rn of the ground equipment
The oscillation frequency shifts to one of the oscillation frequencies f1 to Fn selected by . Now, if the oscillation frequency in this case is f1, then
As a result, only the selective amplifier circuit SAl outputs the output signal a of the ゜1゜ level, while the output signal of the selective amplifier circuit SAO is no longer generated.

Therefore, the main relay MR falls and complementary output signals A and i are output from the hold circuit HDl, and these output signals A and a are transmitted to the first series coater section CDl and the second series coater section CDl.
Common human power is applied to the series coater section CD2. As a result, the first sequence coater unit CDl and the second sequence coater unit CD2 transfer the first information A and the second information A to the corresponding first sequence logic unit LGl and second sequence logic unit LG2, respectively.
supply to. Then, the first series logic unit LGl and the second
The sequence logic unit LG2 judges whether the input first information A and second information λ have a valid code structure, and also determines whether the first information A and second information x are combined with other input information. It is determined whether or not the information is complex information. The validity of the first information A and the second information A should be determined independently, and if the result is that the information is valid, the first information A and the second information A should be used first. After being processed in the same manner as in the embodiment shown in FIG. 5, it is supplied to register RG3 in FIG.

As a result, an output signal 0U1 similar to the embodiment shown in FIG.
~0U0 can be obtained. As is clear from the above explanation, when this invention is applied to a point information detection device,
Output information for point information can be quickly output, and safe operation can always be ensured in the event of an abnormality. Furthermore, since the above-described information processing is performed using an integrated circuit, the device can be miniaturized, which is extremely advantageous when mounted on a vehicle. As explained above, the information processing device according to the present invention uses an integrated circuit to first set the first redundant code structure in a complementary relationship based on input information.
Create combination information and second combination information, then create third combination information by exclusive OR processing of the first combination information and second combination information, and combine this third combination information with the first combination information. By outputting in complementary time relation,
Among combination information consisting of n bits, combination information in which r bits change in an alternating current manner is obtained, which is converted into a direct current and then decoded to send output information corresponding to input information.

Therefore, output information can be quickly output in response to input information, and safety can always be ensured in the event of an abnormality.

In particular, when the above processing is divided into two systems, one system performs the function of constantly monitoring the processing of the other system, demonstrating the advantage of further improving the fail-safe logic function, and detecting point information in automatic train stopping devices. If applied to equipment that must always be on the safe side in abnormal situations, such as equipment, it will be extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an output signal of the clock oscillator in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the drive circuit in FIG. 1. FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. 1, FIG. 5 is a circuit diagram showing another embodiment of the invention, and FIG. 6 is the embodiment shown in FIG. 5. 7 is a block diagram showing an example of a point information detection device to which the present invention is applied, and FIG. 8 is a time chart for explaining the operation of the first series logic section and the second series logic section in FIG. FIG. 3 is a block diagram showing the internal configuration. 1゜゜“゜゜゛Inverter, 2, 3... Coater, 4, 5, 11... Register, 6...
Exclusive OR circuit, 8, 9...gate, 10.
...OR gate, 12...Drive circuit, 1
3...Decoder, WC...Resonance coil, PC...Pickup coil, 0S...
・゛Oscillation amplifier circuit, SAO-SAn...Selective amplifier circuit.

Claims (1)

[Claims] 1. Any input information having an m-bit (m≧1) configuration is divided into first information and second information having a mutually complementary n-bit (n>2) configuration.
an information converting means for converting into information and outputting it; an arithmetic means for performing exclusive OR processing of the first information and the second information; and an information converting means for converting and outputting the first information into information; a gate means for alternately outputting information, an information holding means for holding the output information of the gate means in a direct current manner, and a decoding means for decoding the information held by the information holding means; 2 information is r bits (2≧r<
n), the r bits out of the n bits alternately repeat binary levels from the gate means, and this combination information is held in direct current by the information holding means. The information processing apparatus is characterized in that the information is then decoded by the decoding means, and the decoded output is sent out as output information corresponding to the input information. 2. Input information of arbitrary m-bit (m≧1) configuration is divided into first information and second information of n-bit (n>2) configuration that are complementary to each other.
a first and second series information conversion means for converting and outputting two series of information; and a means for converting first and second series information into information;
two series of first and second series information converting means for performing exclusive OR processing with the information, and the output information of the arithmetic means of each series and the first information are alternately arranged in a complementary time relationship for each series. The first information and the 2 information is r bits (2≦
The combination information is expressed as a combination of r<n), and the gate means obtains combination information in which r bits out of n bits alternately repeat binary levels, and this combination information is stored in a direct current manner by the information holding means. An information processing apparatus characterized in that the information is temporarily held and then decoded by the decoding means, and the decoded output is sent out as output information corresponding to the input information.