JPS5958844U - System switching circuit - Google Patents

System switching circuit

Info

Publication number
JPS5958844U
JPS5958844U JP1982155590U JP15559082U JPS5958844U JP S5958844 U JPS5958844 U JP S5958844U JP 1982155590 U JP1982155590 U JP 1982155590U JP 15559082 U JP15559082 U JP 15559082U JP S5958844 U JPS5958844 U JP S5958844U
Authority
JP
Japan
Prior art keywords
input terminal
nand circuit
power supply
resistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982155590U
Other languages
Japanese (ja)
Inventor
近藤 強司
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP1982155590U priority Critical patent/JPS5958844U/en
Publication of JPS5958844U publication Critical patent/JPS5958844U/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Receiver Circuits (AREA)
  • Electronic Switches (AREA)
  • Power Sources (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のリセット回路を示す回路図、第2図a、
  b、  cは、第1図の回路の動作信号波形図、第
3図はこの考案の一実施例を示す回路図、第4図a ”
−eは第3図の回路の動作信号波形図である。 21・・・電源入力端子、22・・・ナンド回路、24
・・・ダイオード、25,28’、29,31.Ro”
”抵抗、26 、Co・・・コンデンサ、27,30・
・・トランジスタ、A・・・電源の瞬時断検出手段。
Figure 1 is a circuit diagram showing a conventional reset circuit, Figure 2a,
b, c are operating signal waveform diagrams of the circuit in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of this invention, and Fig. 4 a.
-e is an operating signal waveform diagram of the circuit of FIG. 3. 21...Power input terminal, 22...NAND circuit, 24
...Diode, 25, 28', 29, 31. “Ro”
"Resistor, 26, Co... Capacitor, 27, 30.
...Transistor, A...Means for detecting instantaneous interruption of power supply.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)第1入力端に積分回路を介してシステム電源の入
力端子が接続されたナンド回路と、このナンド回路の第
2入力端と前記システム電源の入力端子間に接続され、
前記システム電源によって充電されるコンデンサを有し
、前記システム電源の電位が瞬間的な断により所定電位
よりも降下したときに前記コンデンサを電源として機能
し、前記第2入力端に負のパ/レスを印加して前記ナン
ド回路の出力端に切換パルスを発生させる電源の瞬時断
検出手段とを具備したことを特徴とするシステム切換回
路。
(1) a NAND circuit whose first input terminal is connected to the input terminal of the system power supply via an integrating circuit; and a NAND circuit connected between the second input terminal of the NAND circuit and the input terminal of the system power supply,
It has a capacitor that is charged by the system power supply, the capacitor functions as a power supply when the potential of the system power supply drops below a predetermined potential due to a momentary disconnection, and the second input terminal is connected to a negative resistor. and a means for detecting an instantaneous power interruption for generating a switching pulse at the output end of the NAND circuit by applying a switching pulse to the output terminal of the NAND circuit.
(2)前記電源の瞬時断検出手段は、前記システムの電
源入力端にアノードが接続されコレクタが、第1の抵抗
及び前記コンデンサを介して接地されたダイオードと、
前記ダイオードのカソードがエミッタに接続され、ベー
スに第2の抵抗を介して前記電源入力端が接続され、コ
レクタが第3の抵抗を介して接地された第1のトランジ
スタと、この第1のトランジスタのコレクタにベースが
接続され、エミッタが接地きれ、コレ    ′フタが
第4の抵抗を介して前記電源入力端に接゛続されるとと
もに前記ナンド回路の第2入力端に接続された第2のト
ランジスタとを具備したことを特徴とする実用新案登録
請求の範囲第1項記載のシステム切換回路。
(2) The instantaneous power interruption detection means includes a diode whose anode is connected to the power input terminal of the system and whose collector is grounded via the first resistor and the capacitor;
a first transistor in which the cathode of the diode is connected to the emitter, the power input terminal is connected to the base through a second resistor, and the collector is grounded through a third resistor; The base is connected to the collector of the NAND circuit, the emitter is grounded, the base is connected to the power supply input terminal via the fourth resistor, and the second cap is connected to the second input terminal of the NAND circuit. A system switching circuit according to claim 1, characterized in that the system switching circuit comprises a transistor.
JP1982155590U 1982-10-14 1982-10-14 System switching circuit Pending JPS5958844U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982155590U JPS5958844U (en) 1982-10-14 1982-10-14 System switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982155590U JPS5958844U (en) 1982-10-14 1982-10-14 System switching circuit

Publications (1)

Publication Number Publication Date
JPS5958844U true JPS5958844U (en) 1984-04-17

Family

ID=30343589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982155590U Pending JPS5958844U (en) 1982-10-14 1982-10-14 System switching circuit

Country Status (1)

Country Link
JP (1) JPS5958844U (en)

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