JPS58166112U - Mute pulse generation circuit - Google Patents

Mute pulse generation circuit

Info

Publication number
JPS58166112U
JPS58166112U JP6126882U JP6126882U JPS58166112U JP S58166112 U JPS58166112 U JP S58166112U JP 6126882 U JP6126882 U JP 6126882U JP 6126882 U JP6126882 U JP 6126882U JP S58166112 U JPS58166112 U JP S58166112U
Authority
JP
Japan
Prior art keywords
generation circuit
pulse generation
transistor
load
mute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6126882U
Other languages
Japanese (ja)
Inventor
白木 武志
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP6126882U priority Critical patent/JPS58166112U/en
Publication of JPS58166112U publication Critical patent/JPS58166112U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来のミュートパルス発生回路の一例を示す
回路図、第2図は、第1図における各部電圧の電源オン
時とオフ時における変化を示す波形図、第3図は、本考
案の一実施例を示す回路図、第4図は、−第3図におけ
今冬部電圧の電源オン時とオフ時における変化を示す波
形図、第5図は本考案の他の実施例を示す回路図、第6
図はその各部電圧の変化を示す波形図である。    
  −1,8・・・・・・コンデンサ、3・・・・・・
トランジスタ、4.23・・・・・・抵抗、11.14
・:・・・・定電圧電源回路、12・・・・・・インピ
ーダンスの大きい負q、15・・・・・・インピーダン
スの小さい負荷、21.22・・・・・・ダイオード。
FIG. 1 is a circuit diagram showing an example of a conventional mute pulse generation circuit, FIG. 2 is a waveform diagram showing changes in the voltages of each part in FIG. 1 when the power is turned on and off, and FIG. FIG. 4 is a circuit diagram showing one embodiment of the present invention; FIG. 4 is a waveform diagram showing changes in the winter voltage in FIG. Circuit diagram, 6th
The figure is a waveform diagram showing changes in voltage at each part.
-1, 8... Capacitor, 3...
Transistor, 4.23... Resistor, 11.14
.: Constant voltage power supply circuit, 12... Negative q with large impedance, 15... Load with small impedance, 21.22... Diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子装置番り荷として駆動する2つ以上の電源を有し、
その電圧がほとんど同じ場合、電源オン時に立上りの早
い第1電源と負荷との接続点とトランジスタのエミッタ
を抵抗を介して接続し、電源オフ時に立下りの早い第2
電源と負荷との接続点とトランジスタのべ一長を接続1
、前記トランジスタのコレクタから一ミュート出力を得
ることを特徴とするミュートパルス発生回路。
It has two or more power supplies that drive the electronic device as a load,
If the voltages are almost the same, connect the connection point between the first power supply and the load, which rises quickly when the power is turned on, and the emitter of the transistor through a resistor, and
Connect the connection point between the power supply and load and the total length of the transistor 1
, a mute pulse generating circuit characterized in that one mute output is obtained from the collector of the transistor.
JP6126882U 1982-04-28 1982-04-28 Mute pulse generation circuit Pending JPS58166112U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6126882U JPS58166112U (en) 1982-04-28 1982-04-28 Mute pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6126882U JPS58166112U (en) 1982-04-28 1982-04-28 Mute pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS58166112U true JPS58166112U (en) 1983-11-05

Family

ID=30071474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6126882U Pending JPS58166112U (en) 1982-04-28 1982-04-28 Mute pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS58166112U (en)

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