JPS5958833A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5958833A JPS5958833A JP57169392A JP16939282A JPS5958833A JP S5958833 A JPS5958833 A JP S5958833A JP 57169392 A JP57169392 A JP 57169392A JP 16939282 A JP16939282 A JP 16939282A JP S5958833 A JPS5958833 A JP S5958833A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- wire
- lead frame
- semiconductor device
- iron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45647—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.
半導体装置は、図に示すように、リードフレームlに半
導体ペレット2が取付けられ、リードフレーム1のリー
ドと半導体ペレット2の’t4fiとをワイヤ3で接続
してなる。As shown in the figure, the semiconductor device has a semiconductor pellet 2 attached to a lead frame 1, and the leads of the lead frame 1 and 't4fi of the semiconductor pellet 2 are connected by wires 3.
前記リードフレーム1は、一般には銅、コバール材の表
面に金又は銀メッキ処理を施し、ワイヤ3との接続を良
好にしている。しかしながら、リードフレーlh i
gc金又は銀メッキを施すことは、金又は銀が高価であ
るので、半導体装置がコスト高になる。The lead frame 1 is generally made of copper or Kovar material, and its surface is plated with gold or silver to improve the connection with the wire 3. However, lead frame lh i
Applying gc gold or silver plating increases the cost of the semiconductor device since gold or silver is expensive.
そこで最近、特開昭56−93338号公報に示すよう
に、銅又は銅合金よりなるリードフレームに直接、即ち
表面処理を行わない状態で半導体ペレット及びワイヤの
ホンディングを行うことが行われている。しかしながら
、銅又は銅合金材だけでは表面が硬く、また表面が黒ず
んで酸化膜ができるので、ワイヤの接続が弱く、ボンデ
ィングされたワイヤがはがれることが時々発生する。Recently, as shown in Japanese Unexamined Patent Publication No. 56-93338, semiconductor pellets and wires have been bonded directly to lead frames made of copper or copper alloys, that is, without surface treatment. . However, if only copper or copper alloy material is used, the surface is hard, and the surface becomes dark and an oxide film is formed, so that the wire connection is weak and the bonded wire sometimes comes off.
本発明は上記従来技術の欠点に鑑みなされたもので、品
質の優れた半導体装置を提供することを目的とする。The present invention was made in view of the above-mentioned drawbacks of the prior art, and it is an object of the present invention to provide a semiconductor device with excellent quality.
本発明は銅又は銅系合金もしくは鉄又は鉄系合金のリー
ドフレームの表面(こ銅メツキ処理を施したことを特徴
とする。The present invention is characterized in that the surface of a lead frame made of copper or a copper-based alloy, or iron or an iron-based alloy is subjected to copper plating treatment.
銅又は銅系合金(例えば銅−錫合金、銅−錫一燐合金)
もしくは鉄又は鉄系合金(例えば鉄−ニッケル合金、鉄
−ニッケルーコバルト合金)の基材そのものの表面は硬
いが、この表面に銅メツキ処理を施すことにより、リー
ドフレームの表面は軟質相になる。そこで、ワイヤはこ
の軟質材よりなる銅メツキ部分に接続されるので、接続
の強度が増加し、ワイヤのはがれがなくなる。またリー
ドフレームは銅メッキされているので、表面の酸化が防
止さイ1、この点からもワイヤの接続が強固になる。Copper or copper-based alloys (e.g. copper-tin alloy, copper-tin monophosphorus alloy)
Alternatively, the surface of the base material itself of iron or iron-based alloys (e.g. iron-nickel alloy, iron-nickel-cobalt alloy) is hard, but by applying copper plating to this surface, the surface of the lead frame becomes a soft phase. . Therefore, since the wire is connected to the copper-plated portion made of this soft material, the strength of the connection is increased and the wire does not come off. Also, since the lead frame is copper plated, the surface is prevented from oxidizing1, which also makes the wire connection stronger.
なお、前記銅メツキ処理はリードフレームの全面に行っ
てもよいが、少なくともワイヤが接続されるリードのみ
(こ施せは十分である。またワイヤの接続は、従来と同
様に窒素ガス等の不活性ガス雰囲気中で行うことにより
、更に良好なボンディングが行えることは勿論である。The copper plating process may be applied to the entire surface of the lead frame, but it is sufficient to apply the copper plating process only to the leads to which the wires are connected. Of course, even better bonding can be achieved by performing the bonding in a gas atmosphere.
以上の説明から明らかな如く、本発明によれば、銅又は
銅系合金もしくは鉄又は鉄系合金よりなるリードフレー
ムの表面に銅メツキ処理が施してなるので、τツイヤ接
続の強度が増大し、ワイヤはが第1がなくなり、品質が
向上する。As is clear from the above description, according to the present invention, since the surface of the lead frame made of copper, copper-based alloy, iron or iron-based alloy is subjected to copper plating, the strength of the τ-twir connection is increased, The first wire is eliminated and the quality is improved.
【図面の簡単な説明】
図は半導体装置の概略断面図である。
1・・・リードフレーム、 2・・・半4体ベレッ
ト、3・・・ワイヤ。BRIEF DESCRIPTION OF THE DRAWINGS The figure is a schematic cross-sectional view of a semiconductor device. 1...Lead frame, 2...Half-four bullets, 3...Wire.
Claims (1)
フレームのリードと半導体ベレットの’a極とをワイヤ
で接続してなる半導体装置において、前記リードフレー
ムは銅又は銅系合金もしくは鉄又は鉄系合金よりなり、
少なくともワイヤが接続されるリードの表面−こ銅メツ
キ処理を施してなることを特徴とする半導体装置。In a semiconductor device in which a semiconductor pellet is attached to a lead frame, and the lead of the lead frame and the 'a pole of the semiconductor pellet are connected by a wire, the lead frame is made of copper or a copper-based alloy, or iron or an iron-based alloy,
A semiconductor device characterized in that at least the surface of a lead to which a wire is connected is copper-plated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57169392A JPS5958833A (en) | 1982-09-28 | 1982-09-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57169392A JPS5958833A (en) | 1982-09-28 | 1982-09-28 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5958833A true JPS5958833A (en) | 1984-04-04 |
JPH0141028B2 JPH0141028B2 (en) | 1989-09-01 |
Family
ID=15885744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57169392A Granted JPS5958833A (en) | 1982-09-28 | 1982-09-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5958833A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60225450A (en) * | 1984-04-24 | 1985-11-09 | Furukawa Electric Co Ltd:The | Manufacture of semiconductor device |
JPS60240149A (en) * | 1984-05-15 | 1985-11-29 | Sharp Corp | Semiconductor device |
JPS6180844A (en) * | 1984-09-28 | 1986-04-24 | Furukawa Electric Co Ltd:The | Basic wire for semiconductor lead frame |
JPS61201762A (en) * | 1985-03-05 | 1986-09-06 | Furukawa Electric Co Ltd:The | Manufacture of bar material for electronic equipment part |
JPS62213269A (en) * | 1986-03-14 | 1987-09-19 | Hitachi Cable Ltd | Lead frame for semiconductor |
US4707724A (en) * | 1984-06-04 | 1987-11-17 | Hitachi, Ltd. | Semiconductor device and method of manufacturing thereof |
DE3828700A1 (en) * | 1987-09-16 | 1989-04-06 | Nat Semiconductor Corp | COPPER PLATED PAPER FRAME FOR SEMICONDUCTOR PLASTIC HOUSING |
JPH05283596A (en) * | 1992-03-14 | 1993-10-29 | Kyushu Hitachi Maxell Ltd | Lead frame of semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55138246A (en) * | 1979-04-13 | 1980-10-28 | Toshiba Corp | Manufacture of semicondoctor device |
JPS5678357U (en) * | 1979-11-09 | 1981-06-25 | ||
JPS57109350A (en) * | 1980-12-26 | 1982-07-07 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-09-28 JP JP57169392A patent/JPS5958833A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55138246A (en) * | 1979-04-13 | 1980-10-28 | Toshiba Corp | Manufacture of semicondoctor device |
JPS5678357U (en) * | 1979-11-09 | 1981-06-25 | ||
JPS57109350A (en) * | 1980-12-26 | 1982-07-07 | Toshiba Corp | Semiconductor device |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60225450A (en) * | 1984-04-24 | 1985-11-09 | Furukawa Electric Co Ltd:The | Manufacture of semiconductor device |
JPH0558259B2 (en) * | 1984-04-24 | 1993-08-26 | Furukawa Electric Co Ltd | |
JPS60240149A (en) * | 1984-05-15 | 1985-11-29 | Sharp Corp | Semiconductor device |
US4707724A (en) * | 1984-06-04 | 1987-11-17 | Hitachi, Ltd. | Semiconductor device and method of manufacturing thereof |
JPS6180844A (en) * | 1984-09-28 | 1986-04-24 | Furukawa Electric Co Ltd:The | Basic wire for semiconductor lead frame |
JPH0160948B2 (en) * | 1984-09-28 | 1989-12-26 | Furukawa Electric Co Ltd | |
JPS61201762A (en) * | 1985-03-05 | 1986-09-06 | Furukawa Electric Co Ltd:The | Manufacture of bar material for electronic equipment part |
JPS62213269A (en) * | 1986-03-14 | 1987-09-19 | Hitachi Cable Ltd | Lead frame for semiconductor |
DE3828700A1 (en) * | 1987-09-16 | 1989-04-06 | Nat Semiconductor Corp | COPPER PLATED PAPER FRAME FOR SEMICONDUCTOR PLASTIC HOUSING |
DE3828700C2 (en) * | 1987-09-16 | 2002-04-18 | Nat Semiconductor Corp | Copper plated lead frame for semiconductor plastic packages |
JPH05283596A (en) * | 1992-03-14 | 1993-10-29 | Kyushu Hitachi Maxell Ltd | Lead frame of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0141028B2 (en) | 1989-09-01 |
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