JPS63102247A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS63102247A JPS63102247A JP24723986A JP24723986A JPS63102247A JP S63102247 A JPS63102247 A JP S63102247A JP 24723986 A JP24723986 A JP 24723986A JP 24723986 A JP24723986 A JP 24723986A JP S63102247 A JPS63102247 A JP S63102247A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead
- tin
- lead frame
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 31
- 239000011347 resin Substances 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 21
- 239000000956 alloy Substances 0.000 claims abstract description 21
- 238000002844 melting Methods 0.000 claims abstract description 9
- 230000008018 melting Effects 0.000 claims abstract description 9
- 239000011247 coating layer Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 abstract description 17
- 238000007747 plating Methods 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 239000004332 silver Substances 0.000 abstract description 4
- 238000005452 bending Methods 0.000 abstract description 2
- 230000007797 corrosion Effects 0.000 abstract description 2
- 238000005260 corrosion Methods 0.000 abstract description 2
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000004927 fusion Effects 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は樹脂封止型半導体装置に関し、特に信頼性が高
く、作業性も良好な半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a resin-sealed semiconductor device, and particularly to a semiconductor device with high reliability and good workability.
〈従来の技術〉
樹脂封止型半導体装置に用いるソートフレームは、第３
図に一部を断面図で示すように、４２合金（Ｆｅ、 Ｎ
ｉ合金）コバール（Ｆｅ、Ｎｉ、Ｃｏ合金）、銅あるい
は銅合金からなるリードフレームに、必要に応して、素
子固定部３やワイヤボンデインク部９にＡｕや八ｇのめ
っきを部分的に施したものが一般的に用いられている。<Prior art> The sorting frame used for resin-sealed semiconductor devices is
42 alloy (Fe, N
i alloy) On a lead frame made of Kovar (Fe, Ni, Co alloy), copper or copper alloy, if necessary, partially plate Au or 8g on the element fixing part 3 and wire bonding ink part 9. Those that have been applied are generally used.
このようなリードフレームを用いた従来の半導体装置は
、リードフレーム１と封止樹脂７との接着力が不足した
り、あるいはアウターリート部１１の曲げ加工時の応力
などによりすき間か発生したりして、インナーリード部
２と樹脂７の界面を通して、水分か浸入し、半導体素子
４表面のＡｌ線５などか腐食したり、素子特性の低丁な
と問題があった。In conventional semiconductor devices using such lead frames, the adhesion between the lead frame 1 and the sealing resin 7 may be insufficient, or gaps may occur due to stress during bending of the outer lead portion 11. Therefore, there is a problem that moisture infiltrates through the interface between the inner lead portion 2 and the resin 7, corrodes the Al wire 5 on the surface of the semiconductor element 4, and deteriorates the characteristics of the element.
このような問題から封止樹脂とリードフレームの接着性
を良くするため、インナーリード部の形状（特開昭６０
−２６１１６１号ではリードフレームに穴、あるいは溝
を設ける、特開昭５８−１４２５５４号ではインナーリ
ード部に突起を設ける、特開昭５９−１７７９５２号、
特開昭５９−５００３４０号ではインナーリート部にス
リットを設けるなど）を改良したり、さらにはインナー
リード部表面に樹脂との接着性の良好な金属被覆層を設
ける（Ａｌ１層を設ける、金属酸化物層（特開昭６０−
６０７４２号、特開昭６１−３４９６１号）を設ける）
などの改良が行なわれている。In order to improve the adhesiveness between the sealing resin and the lead frame due to this problem, the shape of the inner lead part (Japanese Patent Laid-Open No. 60
In JP-A-261161, a hole or groove is provided in the lead frame, in JP-A-58-142554, a protrusion is provided in the inner lead part, in JP-A-59-177952,
In JP-A No. 59-500340, improvements were made (such as providing slits in the inner lead part), and furthermore, a metal coating layer with good adhesion to resin was provided on the surface of the inner lead part (providing an Al1 layer, metal oxidation, etc.). Material layer (Unexamined Japanese Patent Publication 1986-
No. 60742, JP-A No. 61-34961)
Improvements are being made.
このうち、インナーリード部形状を改良する手法は実際
に実施されている例は多い。しかし、金属被覆層を設け
た方法は半導体の信頼性に対しては十分満足するレベル
ではなく、より一層の特性向上が望まわていた。さらに
、別の問題として、封止樹脂をモールドした後、モール
ドパリが発生するか、このパリがリード部と樹脂との接
着性が改良された結果、パリ取り作業が難しくなり、生
産性あるいは歩溜りを低下させ、コスト上昇の原因とな
っていた。Among these methods, there are many examples in which methods for improving the shape of the inner lead portion are actually implemented. However, the method of providing a metal coating layer does not provide a sufficiently satisfactory level of semiconductor reliability, and further improvement in characteristics has been desired. Furthermore, another problem is that after molding the sealing resin, mold patter occurs, or this pall improves the adhesion between the lead part and the resin, making it difficult to remove the plash, reducing productivity and speed. This lowered the storage capacity and caused an increase in costs.
〈発明が解決しようとする問題点〉
本発明の目的は前記した従来技術の欠点を解消し、樹脂
封止型半導体装置の信頼性を向上させるとともに半導体
組立の作業性を向上させることができる新規な半導体装
置を提供することにある。<Problems to be Solved by the Invention> The purpose of the present invention is to solve the above-mentioned drawbacks of the prior art, improve the reliability of resin-sealed semiconductor devices, and improve the workability of semiconductor assembly. The object of the present invention is to provide a semiconductor device that is of high quality.
〈問題点を解決するための手段〉
本発明は、リードフレームに装着した半導体素子を樹脂
内に封止してなる樹脂封止型半導体装置において、樹脂
内に封止されるリード部分と樹脂外に露出する部分との
境界を含むリード部分に、錫または錫を含有する低融点
合金よりなる被覆層を設けてなることを特徴とする樹脂
封止型半導体装置を提供する。<Means for Solving the Problems> The present invention provides a resin-sealed semiconductor device in which a semiconductor element mounted on a lead frame is sealed in a resin. Provided is a resin-sealed semiconductor device characterized in that a coating layer made of tin or a low melting point alloy containing tin is provided on a lead portion including a boundary with a portion exposed to the lead portion.
〈発明の構成〉 以下に本発明の好適実施例について説明する。<Structure of the invention> Preferred embodiments of the present invention will be described below.
第１図は本発明の半導体装置の一実施例の平面図を示し
、第２図は同じく一部断面図を示す。FIG. 1 shows a plan view of an embodiment of the semiconductor device of the present invention, and FIG. 2 similarly shows a partially sectional view.
本発明は、リードフレーム１等の半導体装置において、
リード部の樹脂内に封止される部分、すなわちモールド
エリヤ８と、アウターソート部１１等の樹脂外に露出す
る部分との境界を含む部分（モールドライン１２付近の
リード部分）に、錫または錫を含有する低融点合金より
なる被覆層を設けることが特徴である。The present invention provides a semiconductor device such as a lead frame 1,
Tin or tin is applied to the portion of the lead portion sealed in the resin, that is, the portion including the boundary between the mold area 8 and the portion exposed outside the resin such as the outer sorting portion 11 (the lead portion near the mold line 12). It is characterized by providing a coating layer made of a low melting point alloy containing.
錫または錫を含有する低融点合金とは、錫系であって融
点が約３００℃以下の錫または錫合金をいう。Tin or a low melting point alloy containing tin refers to tin or a tin alloy that is tin-based and has a melting point of about 300° C. or less.
こわらは、Ｓｎ、 ５ｎ−Ｐｂを代表例として５ｎ−Ｂ
ｉ、５ｎ−５ｂ 、 ５ｎ−４ｒなどの２元合金をはじ
め５ｎ−Ｐｂ−５ｂ等の３元合金等であってもよい。The stiffness is 5n-B with Sn and 5n-Pb as representative examples.
It may be a binary alloy such as i, 5n-5b, 5n-4r, or a ternary alloy such as 5n-Pb-5b.
被覆層厚みは１〜１０μｓとするのが良い。被覆層はリ
ードフレームの片面に設けてもよく第２図に示すように
両面に設けてもよい。The thickness of the coating layer is preferably 1 to 10 μs. The coating layer may be provided on one side of the lead frame or on both sides as shown in FIG.
錫又は錫を含有する低融点合金層を設ける範囲は、第１
図に、錫系合金層１０として示すような部分的範囲だけ
でなく、リート部の樹脂内に封止される部分と樹脂外に
露出する部分の境界を含むリート部分であればよく、ア
ウターリード部１１全体まで設ける場合も本発明の範囲
である。The range in which tin or a low melting point alloy layer containing tin is provided is the first
In addition to the partial area shown as the tin-based alloy layer 10 in the figure, it is sufficient that the leat part includes the boundary between the part sealed in the resin of the leat part and the part exposed outside the resin, and the outer lead A case in which the entire portion 11 is provided is also within the scope of the present invention.
次に本発明の半導体装置の製造方法の１例をリードフレ
ームの製造について説明する。Next, one example of the method for manufacturing a semiconductor device according to the present invention will be described with respect to manufacturing a lead frame.
リードフレーム１は、４２合金（Ｆｅ−Ｎｉ合金）、コ
バール（Ｆｅ−Ｎｉ−Ｃｏ合金）、銅あるいは銅合金等
の板をプレスまたはエツチングにより、１例として第１
図の形にする。２点鎖線で示すモールドライン１２の内
部が樹脂を封止するモールドエリヤ８であり、素子固定
部３とインナーリード部２がある。モールドライン１３
の外側が樹脂外に露出しているリード部等でありアウタ
ーリード部１１がある。The lead frame 1 is made by pressing or etching a plate of 42 alloy (Fe-Ni alloy), Kovar (Fe-Ni-Co alloy), copper or copper alloy, etc., as an example.
Make it into a diagram. The inside of the mold line 12 indicated by the two-dot chain line is a mold area 8 for sealing resin, and includes the element fixing part 3 and the inner lead part 2. mold line 13
There is an outer lead portion 11, which is a lead portion or the like whose outer side is exposed outside the resin.
まず第２図に示すように、インナーリード部２の先端等
に必要に応じて金、銀などの部分めつき６を施す。First, as shown in FIG. 2, partial plating 6 with gold, silver, etc. is applied to the tips of the inner lead portions 2, etc., if necessary.
次に、モールドライン１２を挟んだリード部に錫または
錫合金の錫系合金層１０を設ける。Next, a tin-based alloy layer 10 of tin or a tin alloy is provided on the lead portion with the mold line 12 in between.
このようにして形成したリードフレームｌを用いて、従
来と同様、半導体素子４を素子固定部３上に接合し、Ａ
ｕ線５によるワイヤボンディングを行い樹脂７で封＋ｈ
する。その後アウターリード部１１を第２図に示すよう
に曲げ加工する。最後に、溶融半田めっき層でアウター
リード部１１に半田めっき層（図示せず）を設けて完成
品とする。Using the lead frame l formed in this way, the semiconductor element 4 is bonded onto the element fixing part 3 in the same way as in the conventional case.
Perform wire bonding with U wire 5 and seal with resin 7+h
do. Thereafter, the outer lead portion 11 is bent as shown in FIG. Finally, a solder plating layer (not shown) is provided on the outer lead portion 11 using a molten solder plating layer to complete the product.
〈実施例〉 以下に実施例により本発明を具体的に説明する。<Example> The present invention will be specifically explained below using Examples.
（実施例）
第１図に示す型のリードフレーム１を銅合金でプレス打
抜きにより製造した。インナーリード部２の先端に銀部
分めっき６を形成した後、モールドライン１２を挟んだ
リード部に、錫９０％鉛１０％の組成からなる融点約２
３０℃の錫系合金層１０を６−の厚さで設けた。(Example) A lead frame 1 of the type shown in FIG. 1 was manufactured from a copper alloy by press punching. After forming the silver partial plating 6 on the tip of the inner lead part 2, the lead part sandwiching the mold line 12 is coated with a material having a melting point of approximately 2.
A tin-based alloy layer 10 at 30° C. was provided with a thickness of 6 mm.
Ｓｉ半導体素子４を素子固定部３上に接合し、Ａｕ線５
でインナーリード部２の先端と半導体素子４をワイヤボ
ンディングし、エポキシ樹脂７でモールドエリア８を封
止した。アクタ−リード部１１を曲げ加工し、ここに溶
融半田めっき層を設けて本発明の樹脂封止型半導体装置
とした。The Si semiconductor element 4 is bonded onto the element fixing part 3, and the Au wire 5 is
Then, the tip of the inner lead portion 2 and the semiconductor element 4 were wire-bonded, and the mold area 8 was sealed with an epoxy resin 7. Actor lead portion 11 was bent and a molten solder plating layer was provided thereon to obtain a resin-sealed semiconductor device of the present invention.
樹脂封止時にモールド金型をあてる部分が、錫系合金層
１０で被覆されていて、リードフレーム材に比べ錫系合
金層は１７３〜１／ｌＯも柔らかく、金型の当接によっ
て、リードフレーム材と金型の間の隙間を埋める効果が
あるので、封止樹脂がモールド金型から「はみ出す（モ
ールドパリと称する）」ことがなくパリ取りが容易とな
り、半導体装置製造の作業性が良好であった。The part to which the mold is applied during resin sealing is covered with a tin-based alloy layer 10, and the tin-based alloy layer is 173 to 1/10 softer than the lead frame material, and the contact of the mold will cause the lead frame to Since it has the effect of filling the gap between the material and the mold, the sealing resin does not "extrude" from the mold (referred to as mold pars), making it easy to remove the mold, improving workability in semiconductor device manufacturing. there were.
また、アウターリード部１１の溶融半田めっき工程で、
モールドライン１２附近の錫系合金層１０が溶融して樹
脂７とリードフレーム１との間の隙間を埋め、樹脂とリ
ードフレーム１の接合が完全となり半導体装置の信頼性
が向上した。In addition, in the molten solder plating process of the outer lead portion 11,
The tin-based alloy layer 10 near the mold line 12 melted and filled the gap between the resin 7 and the lead frame 1, and the bond between the resin and the lead frame 1 was completed, improving the reliability of the semiconductor device.
〈発明の効果〉
本発明の樹脂封止型半導体装置は、樹脂封止するモール
ドライン附近のリード部に柔らかい錫系合金層を有する
ので、樹脂封止時に金型とリード材との密着が完全で、
樹脂が「はみ出す」ことがなくパリ取りが容易で製造作
業性が良い。<Effects of the Invention> The resin-sealed semiconductor device of the present invention has a soft tin-based alloy layer on the lead portion near the mold line to be resin-sealed, so that the mold and lead material are completely adhered to each other during resin-sealing. in,
The resin does not "extrude", making it easy to remove debris and improve manufacturing workability.
従来はモールドバリが大きいため樹脂封止外のリードフ
レーム上に樹脂が付着し、銅をリードフレーム材とした
場合にはアウターリードの半田めっき後の赤肌発生の原
因となった。しかし、本発明ではパリがなくなり赤肌が
皆無となり、リードフレームの耐食性が向上した。Conventionally, large mold burrs caused resin to adhere to the lead frame outside of the resin seal, and when copper was used as the lead frame material, this caused red skin after solder plating of the outer lead. However, in the present invention, there is no flaking, there is no red skin, and the corrosion resistance of the lead frame is improved.
また、アウターリード部の溶融半田めっき時錫系合金層
が溶融して、樹脂とリードフレームのスキ間を埋め、水
分の侵入を抑制する。この結果、樹脂封止型半導体装置
の信頼性を大幅に向上させることができた。Furthermore, during hot-dip solder plating on the outer lead portion, the tin-based alloy layer melts and fills the gap between the resin and the lead frame, thereby suppressing the intrusion of moisture. As a result, the reliability of the resin-sealed semiconductor device could be significantly improved.
第１図は本発明の樹脂封止型半導体装置の１実施例を示
す平面図である。
第２図は本発明の１実施例を示す一部断面図である。
第３図は従来例を示す一部断面図である。
符号の説明
１・・・リードフレーム、２・・・インナーリード部、
３・・・素子固定部、４・−・半導体素子、５＝−Ａｕ
線、６・・・部分めっき、７・・・樹脂、
８・・・モールドエリア、
９・・・ワイヤボンディング部、
１０・・・錫系合金層、１１・・・アウターリード部、
１２・・・モールドライン
ＦＩＧ、１FIG. 1 is a plan view showing one embodiment of the resin-sealed semiconductor device of the present invention. FIG. 2 is a partially sectional view showing one embodiment of the present invention. FIG. 3 is a partial sectional view showing a conventional example. Explanation of symbols 1...Lead frame, 2...Inner lead part,
3... Element fixing part, 4... Semiconductor element, 5=-Au
Wire, 6... partial plating, 7... resin, 8... mold area, 9... wire bonding part, 10... tin-based alloy layer, 11... outer lead part,
12...Mold line FIG, 1
Claims (1)
封止してなる樹脂封止型半導体装置において、樹脂内に
封止されるリード部分と樹脂外に露出する部分との境界
を含むリード部分に、錫または錫を含有する低融点合金
よりなる被覆層を設けてなることを特徴とする樹脂封止
型半導体装置。(1) In a resin-sealed semiconductor device in which a semiconductor element mounted on a lead frame is sealed in a resin, the lead portion includes the boundary between the lead portion sealed in the resin and the portion exposed outside the resin. 1. A resin-sealed semiconductor device comprising: a coating layer made of tin or a low melting point alloy containing tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24723986A JPS63102247A (en) | 1986-10-17 | 1986-10-17 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24723986A JPS63102247A (en) | 1986-10-17 | 1986-10-17 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63102247A true JPS63102247A (en) | 1988-05-07 |
Family
ID=17160522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24723986A Pending JPS63102247A (en) | 1986-10-17 | 1986-10-17 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63102247A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1524693A1 (en) | 2003-10-13 | 2005-04-20 | Infineon Technologies AG | Leadframe being protected against corrosion |
| CN101834256A (en) * | 2009-03-10 | 2010-09-15 | Lg伊诺特有限公司 | Light emitting device package |
| JP2010212691A (en) * | 2009-03-10 | 2010-09-24 | Lg Innotek Co Ltd | Light emitting element package |
| US8503189B2 (en) | 1997-12-16 | 2013-08-06 | Renesas Electronics Corporation | Pb-free solder-connected structure and electronic device |
-
1986
- 1986-10-17 JP JP24723986A patent/JPS63102247A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8503189B2 (en) | 1997-12-16 | 2013-08-06 | Renesas Electronics Corporation | Pb-free solder-connected structure and electronic device |
| EP1524693A1 (en) | 2003-10-13 | 2005-04-20 | Infineon Technologies AG | Leadframe being protected against corrosion |
| US7432584B2 (en) | 2003-10-13 | 2008-10-07 | Infineon Technologies, Ag | Leadframe for use in a semiconductor package |
| CN101834256A (en) * | 2009-03-10 | 2010-09-15 | Lg伊诺特有限公司 | Light emitting device package |
| JP2010212691A (en) * | 2009-03-10 | 2010-09-24 | Lg Innotek Co Ltd | Light emitting element package |
| US8987775B2 (en) | 2009-03-10 | 2015-03-24 | Lg Innotek Co., Ltd. | Light emitting device package |
| JP2015159321A (en) * | 2009-03-10 | 2015-09-03 | エルジー イノテック カンパニー リミテッド | light emitting device package |
| US9318677B2 (en) | 2009-03-10 | 2016-04-19 | Lg Innotek Co., Ltd. | Light emitting device package |
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