JPS595783A - Preventing circuit for remote control malfunction - Google Patents

Abstract

PURPOSE:To prevent a remote control system which changes channels of television by utilizing infrared rays, etc., from malfunctioning owing to a noise in a received infrared-ray remote control signal, by clamping a circuit when the noise is detected. CONSTITUTION:To detect an infrared-ray noise generated between pulses of the remote control signal of a remote controller which utilizes infrared rays for changing channels, etc., of television, a noise detection period pulse is generated between those pulses for detecting a noise and when the noise is detected, a remote control signal received thereafter is made ineffective. For this purpose, a noise detection period pulse generating means consisting of a timing generating circuit 20 is provided to detect the noise by the noise detection period pulse, and the circuit is clamped to inhibit respective pulses of the received remote control signal from being transmitted to a trailing signal reception control circuit. Further, the end of one word is repeated. Consequently, even if a noise originating from external infrared rays is mixed in the received remote control signal, malfunction due to the transmission to the remote control signal to the trailing signal receiving circuit is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a remote control malfunction prevention circuit, more specifically, a remote control system that uses infrared rays to switch the tunnel of a television. This invention relates to a remote control malfunction prevention circuit that prevents malfunctions.

It is very convenient to freely control TV channels etc. remotely using an infrared remote control device, but such a remote control device that uses infrared rays is susceptible to infrared noise from, for example, fluorescent lights. It may get mixed into the remote control system and cause it to malfunction. In addition, such infrared noise is generated not only from fluorescent lamps, but also from various lighting equipment that have been developed recently, and even from automatic focusing using infrared rays in cameras, etc. Some cameras also detect the infrared signals generated by these cameras as noise, which can cause them to malfunction.

An object of the present invention is to provide a remote control malfunction prevention circuit that prevents malfunctions caused by the above-mentioned external infrared noise and operates accurately without malfunctions.

Next, before explaining the present invention with reference to illustrated embodiments, an outline of the configuration of a remote control signal in such an infrared remote control device will be explained.

In a remote control device that uses infrared rays to switch TV channels, for example, one word of the remote control signal consists of seven series pulses P1 to P7, as shown in the received remote control control signal in Fig. 2. , consisting of six pulse intervals between each pulse,
jolt, I determined by the length of the pulse interval
f I Consists of 6 bits encoded with 11 bits. This 1-word remote control signal made up of 6 bits can be used to send out TV channel information, raise/lower the volume, turn mute on/off, turn up/down the hair channel, etc. It constitutes various control signals that perform the following. And J: Specifically, bit 110 IT is defined as 2 ms''c interval between two pulses, and bit 1'' is defined as 4 ms interval between pulses. On the receiving side, the interval between pulses is 0.1 ms to 3.
．． Bits in the range of 2 ms are judged as bits "0", and the interval between pulses is between 3.2 ms and 6.2 ms.
Anything in the 4 ms range is judged as a pid '1'' and processed.The transmitting side is configured to transmit the 1-word remote control signal configured in this way multiple times, for example, 5 times. The receiving side receives two control signals transmitted five times in this way, and if at least two of them are the same, it is determined to be a legitimate signal and the remote control device is operated. In order to distinguish between each remote control control signal when transmitting a 6-bit remote control control signal five times as shown in FIG. For example, 48n+s is set as the time interval for transmitting the remote control control signal. Then, the receiving side transmits the remote control signal multiple times (for example, 5 times) at intervals of 48m5la.
When receiving the transmitted remote control control signals, if there is at least 6.4 ms between each remote control control signal, it is determined that the end of one word of the remote control control signal is reached, The remote control control signal is determined and received word by word, and at least two of them are received.
If the two or more words are the same, the remote controller v control code is determined to be correct and control is performed.

It is in the remote control control signal configured in this manner that there is a risk that infrared noise from the outside may be superimposed on the signal and cause the receiver to malfunction. This is a case where noise occurs between pulses.

Therefore, in the present invention, in order to detect the external infrared noise generated in this way, as will be explained in detail below using the drawings, in order to detect the infrared noise generated between the pulses, A pulse is generated during the noise detection period between the two pulses, and noise is detected using this pulse. If there is noise, the remote control control signal received after that is invalidated.

The smartphone controller malfunction prevention circuit of the present invention, not shown in FIG. The signal is input terminal T1
The received signal is input to the The remote control control signal input to this input terminal lower 1 is supplied to one input terminal of a signal gate 2 consisting of a link circuit 1 to a circuit (hereinafter abbreviated as a NAND circuit), and the output of this signal gate 2 is a resistor. Tran via R1, Sister Ding r
The signal is supplied to the base of the transistor Tr, and is supplied from the collector of the transistor Tr to the remote control control signal receiving device via the output terminal 1-2. And in this case,
The output waveform of the remote control control signal outputted from this output terminal T2 and the waveform of the remote control control signal inputted to the input terminal T1 are the same waveform. Further, the output of the signal gate 2 is supplied to one input of a noise detection gate (8) which is constituted by a NAND circuit, and the output of this noise detection gate 8 is supplied to one input of the NΔAND circuit (5) which constitutes a flip 70 block for noise gate clamping. The output of the NAND circuit 6 of this noise gate clamp flip-flop is supplied to one input of the NAND circuit 5 on one side of the noise gate clamp. It is connected to the other input terminal of gate 2, and when this noise gate clamp flip-flop is set due to the occurrence of noise, it inhibits signal gate 2 and clamps the output of gate 1-2. Also, at the bottom right of this circuit are NAND circuits 15 and 16, and resistors Rs and R[;
A clock oscillation circuit 19 consisting of a variable resistor VR and a capacitor Go is provided.
A clock signal of 1'Z and a period of 50 μs is generated. Then (NAND circuit 1 of this clock oscillation circuit 19
The clock signal output from 57J1 r is supplied to one input terminal of the timing generation control gate 9 composed of a NAND circuit, and at the same time, it is supplied to one input terminal of the clock gate 13 composed of a NAND circuit. Also supplied.

The output of this clock gate 13 is the NAND circuit 1
4 to the clock input terminal C[- of the timing generation circuit 20. This timing generation circuit 20
For example, μm]D4040C manufactured by NEC Corporation
It is made using an integrated circuit, and consists of a binary counter that counts the clock signal supplied to the clock input horn terminal C1 mentioned above. Then, the output of the counted result of A is generated as a noise detection period pulse from the output terminal Qs, is generated as a reset pulse after 1.0Ills from the output terminal Q1, and is further generated as a reset pulse after 12.8111S from the output terminal Q9. pulses are generated.

Note that this timing generation circuit 20 is operated with the terminal Vss connected to ground and the terminal Voo connected to plus 12V. The output terminal Q5 of the timing generation circuit 20 is connected to the other input terminal of the noise detection gate 1-8, and the noise detection period pulse is supplied to the other input gate of the noise detection gate 8. ing.

Also, the output terminal Q[, of the timing generation circuit 20 is NA
It is connected to one input end of the ND circuit 7, and this N
The other input of the AND circuit 7 is supplied with the output of the NAND circuit 6 forming the noise group 1 to the clamp knob. The output of the NAND circuit 7 is connected to one input terminal of the reset timing selection gate 1 made up of the NAND circuit 1, and the other input terminal of the reset timing selection gate is connected to the output terminal Q9h of the timing generation circuit 20. 12.8II
After IS, a Richts pulse is supplied via the NAND circuit 4. The output of the reset I/timing selection gate 1 is connected to the reset terminal R8 of the timing generation circuit 20 via resistor 1 and 4.
It is connected via the ND circuit 3 to one input terminal of the NΔND circuit 6 that constitutes the above-mentioned noise gate clamp flip-flop, and one of the NA N I) circuits 10 and 12 that constitute the clock gate flip-flop. NA of
It is supplied to one input end of the ND circuit 10. The output of the timing generation control gate 9 is connected to one input of the NAND circuit 12 constituting the clock gate flip-flop.The other input of the timing generation control gate 9 is connected to the -[open signal. The output of the gate 2 is connected to the gate 2. The output of the NAND circuit 12 constituting the clock gate flip-flop is connected to the other input of the clock gate 1-13. The terminal R8 is grounded via the -1 capacitor C1, and when the power is turned on, the reset terminal R8 is grounded via the capacitor C1.
8 is grounded, and this timing generation circuit 20 is reset. Furthermore, the terminal T1 is connected to plus 12V via a resistor R1, the base of the transistor lr is grounded via a resistor R2, and the collector is connected to plus 12V via a resistor R3. There is.

The remote control malfunction prevention circuit of the present invention is configured as described above. Next, its operation will be explained with reference to FIGS. 2 and 3.

First, a normal case where there is no noise in the remote control control signal sent as an infrared signal will be described. In this case, the remote control control signal received at the input terminal T1 is as shown in the received remote control control signal in FIG.
One word consists of six pulses P1. P2, P3, P
4, Ps, PIl,.

P7, and consists of a 6-bit signal with six pulse intervals. The pulse width of each pulse is 0.5ms, and if the interval between each pulse is 2IIls, the bit "0"
In this case, as shown in the figure, the information represented by λ'' is received by this one-word remote control signal. The number '010100' is roaring. A one-word remote control control signal configured like this
is sent out repeatedly five times, but in this case, there is an interval of 48 m5 between one remote control control signal and the next one, as shown in the figure. The interval between the last pulse of the control signal and the first pulse of the next remote control control signal is at least 2411
13 or more, and the receiving device that receives it considers various fluctuations and determines that the interval between pulses is 0.1 ms or more and C within 3.2 ms as pit 0'°. 3.2111F+ or more-t-6,
If the interval is within 4 ms, it is determined as PID 1''.If the interval between each word of the remote control signal and the next Norikon control signal is 6.4 ms or more, the previous word's remote control control signal is It is configured so that it is judged as the end of the period.

Such a remote control control signal is repeated five times and input to input terminal 1 of the remote control malfunction prevention circuit shown in Fig. 1, but first, before the signal enters this remote control malfunction prevention circuit, the To explain the initial state of the circuit, as a result of the processing performed before that, first, the NΔN that constitutes the noise gate clamp flip-flop is
The output of the D circuit 5 is in the 0'' state, and the output of the other NANO circuit 6 is in the ``1'' state.
The output of one NAND circuit 10 constituting the flip-flop for 1 is in the 1'' state, and the other NANO circuit 12 is in the "O" state.

The timing generation circuit 20 is naturally in a reset state. The clock oscillation circuit 19 always generates a clock signal from the output of the NAND circuit 15.
This output clock signal is output from the clock gate flip 70.
Since the clock gate 13 is inhibited by the output of the Tsubu's NAND circuit 12, N A N I)
The signal is arranged so that it is not transmitted to the timing generation circuit 20 via the circuit 14. Further, the clock signal supplied to the gate 9 for timing generation control 911 is also inhibited by the "0" signal of the signal gate 2 supplied to the other of the timing generation control meligates 1 to 9, and the clock signal is It is designed so that it is not supplied to 70 tubes. In addition, the above-mentioned signal 2 is supposed to be supplied with a remote control control signal through T1 of one of its input terminals, but if this remote control control signal is not received, this signal will be sent as shown in the figure. The input terminal is in the "1" state, and the other input terminal of the signal gate 2 has an NA constituting a noise gate clamp flip-flop.
Since the "1" output of the ND circuit 6 is supplied, the output terminal of the signal gate 2 is in the 0" state.

As described above, in the initial state, C1 first receives a remote control control signal through input terminal T1 (then, signal gate 2 is activated by the first pulse P2 of A, and its output becomes 1''. As a result, this signal At the same time, the "1" output of the gate 2 is supplied to the signal receiving circuit from the output terminal T2 via the transistor "r", and at the same time, this signal is supplied to the other input terminal of the timing generation control gate 9, and this signal This gate is opened by the "1" output of the gate 2, and the output clock signal of the clock oscillation circuit 19 sets the clock gate flip-flop via the timing generation control gate 9, and the output of the NAND circuit 12 becomes " OI+
to 1''. As a result, the clock gate 13 is in a gated state, and the clock oscillator circuit 19 is now supplied to one terminal of the D-gate.
The clock signal passes through the clock gate 13 and is further supplied to the clock input terminal OL of the timing generation circuit 20 via the NAND circuit 14.The timing generation circuit 20 is operated to count the supplied clock signal. It has become.

As a result, this timing generation circuit 20 has an output terminal Q
5 generates a noise detection period pulse as shown in FIG. 2 and supplies it to the other input terminal of the noise detection gate 8. As can be seen from FIG. 2, the noise detection period pulse generated from the output terminal Q5 of the timing generation circuit 20 is between the pulse of the control signal and the pulse. The external infrared noise generated between these pulses is detected as described above.

First, as explained in this example, if there is no noise, the signal gate 2 will not become 1" during this noise detection period pulse due to this noise, so the output of the noise detection gate 8 will be "1". Because it remains in the output state,
This prevents the noise gate clamp flip-flop composed of the NAND circuits 5 and 6 from being set. Therefore, since the output of the NAND circuit 6 constituting the noise gate clamp flip-flop does not become O'', the signal gate 2 is inhibited from clamping the received remote control control signal. Further, when the noise detection period pulse generated from the output terminal Qs of the timing generation circuit 20 ends, the next output terminal Q etc.
．． After 6ms, when the reset pulse 2 is generated as shown in Figure 2, the output of the NAND circuit 7 becomes 'O', and the 'O' output signal of this NAND circuit 7 becomes NAND.
The signal is supplied to one gate of the NAND circuit 10 of the clock gating flip-flop via circuit 1.3 to reset the clock gating flip-flop. When the clock gate Noritsubu flop is reset, its N
The clock gate is inhibited by the output of the AND circuit 12, and the clock signal from the clock oscillation circuit 19 is no longer supplied to the timing generation circuit 20. On the other hand, the "0°" output signal of the NAND circuit 7 is sent to the timing generation circuit 2 via the reset timing selection gate 1.
0 reset terminal R8 to reset the timing generation circuit 20 and stop its counting operation. In this way, when one pulse P1 of the remote control control signal comes, the clock gate control flop is activated and the timing generation circuit is activated, and when the predetermined operation is completed, the timing generation circuit 20 is activated and the timing generation circuit 20 is activated. When a predetermined operation is completed, a reset pulse generated from the timing generation circuit 20 terminates this series of operations. This operation is repeated every time one pulse arrives, and the output terminal Q5 of the timing generation circuit 20 mentioned above is
The presence or absence of noise between each pulse is detected using the noise detection period pulses generated from the pulse.

The above is a case in which there is no external infrared noise. Next, the operation will be described in the case where external infrared noise is included in the received remote control control signal. As shown in the timing chart in Fig. 3, a noise pulse P is generated next to pulse P2 of the received remote control control signal.
is shown. In Figure 3,
When the first pulse P1 of the -1 control signal is input, the operation is the same as that described with reference to FIG. 2 above.

Then, when the second pulse 2 comes in, the initial operation until the noise in this circuit comes is the same as before: signal gate 2 and timing generation by that pulse P2 The clock gating flip-flop is set via the control gate 9, thereby causing the timing operation of the timing generating circuit 20, and the steps up to the point where the noise detection period pulse is generated from the output terminal Q5 are the same. Then, this noise detection period generation pulse is generated and is supplied to the other input terminal of the noise detection goo]-8, and while this noise detection period pulse is being supplied, the above noise pulse is generated (・As a result, the signal gate 2 momentarily enters the state of r+ 1 ++, and this signal is detected by the noise detection gate 8, which sets the noise gate clamp flip-flop and changes its NA.
The ND circuit 5 is in the form of "1" (7) 11k: 4'
), NANDUJ path 61fi becomes “0” state.

When the noise gate clamp flip flap is set and the output j of the NAND circuit 6 becomes O'',
This "0" output inhibits the signal gate 2,
This clamps the circuit and prevents the remote control control signal coming into the input terminal 1-1 from being transmitted to the reception control circuit via the transistor lr. Also NAN
When the D circuit 6 is in the state of “0'°, this causes the NAN
The D circuit 7 is in a suppressed state, and the reset pulse from the output terminal Qc of the timing generation circuit 20 is supplied to the flip-flops for clock groups 1 to 1 and the flip-flops for the noise gate clan I, so that each nor-bit flop is not re-hit. That's what I do. When the noise gate clamp flip 70 is turned off and this clamp state has elapsed for a predetermined period, where τ is 128m5 in this embodiment, the output terminal Q! of the timing generation circuit 20 is activated. A reset pulse of 1 to 12.8 ms is generated, and this reset pulse resets the noise gate clamp flip-flop and the crack gate flip-flop through the NANO circuit 4.1.3, returning them to the initial state. ing. Note that the signal from which the 12.8m5m reset pulse is generated from the output terminal Q9 of the timing generation circuit 20 is supplied to the reset terminal RS mentioned above via the NAND circuits 4 and 1, so that the timing generation circuit 20 is rehit. It has become. As described above, when the noise gate clamp flip-flop is set and the signal gate 2 is clamped thereby, the received remote control signal is
It remains in an invalid and erased state until the reset pulse is generated after the reset, and is not transmitted from the output terminal T2 to the signal reception control circuit via the transistor 1''.As a result, the signal reception control circuit In this case, the remote control control signal mixed with noise is judged to be incomplete because the number of pulses, that is, the number of bits is insufficient.In the above explanation, the timing generation circuit 20
2, which constitutes the timing generation circuit 20 for the 12.8 ms post-reset pulse generated from the output terminal Q9 of the
From the circuit configuration of the decimal counting circuit, 12.8 is one of them.
1115, and as mentioned above, the same mechanism can be achieved as long as the interval between one word and the control signal is at least 5 or 4 ms, which is the minimum condition. This meaning comes from the fact that, as mentioned above, if the interval between pulses is 6.4 ms or more, it is considered the end of one word, and as shown in (a) above, there is no noise. This causes a clamping operation and the received signal is clamped.
As a result, each pulse of the remote control control signal is not transmitted to the signal receiving circuit via the 1-run sister Tr, thereby notifying the end of one word and preventing reception of a signal containing noise. There is.

As explained above, according to the present invention, the noise detection period pulse generating means is comprised of the timing generation circuit 20, and the noise is detected by applying the noise detection period pulse to the noise detection period pulse, thereby clamping the circuit. Since each pulse of the remote control control signal received is not transmitted to the next stage signal reception control circuit and the end of one word is notified, the external Even if noise generated from infrared rays is mixed in, this noisy remote control control signal is transmitted to the next signal receiving circuit to prevent malfunction.

If there is no noise within the detection period and no noise is detected, the noise detection period pulse generation circuit is reset at the end of the noise detection period so as to immediately return to the noise detection preparation state. If there is noise within the noise detection period, the noise detection period pulse generation circuit is reset when the gate clamp ends.

By selectively using the above two reset periods with and without noise, there is an effect that more accurate noise detection can be performed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a remote control malfunction prevention circuit which does not show an embodiment of the present invention, and FIGS. 2 and 3 are timing charts of the remote control malfunction prevention circuit of FIG. 2... Signal gate (signal receiving circuit), 5.6.
...NAND circuit (flip 1 for noise gate clamp), 8...Noise detection gate, 20...Timing generation circuit'. Applicant Shin Nippon Electric Co., Ltd. Agent Patent Attorney Masu 1) Takeo 43

Claims (1)

[Claims] 1.1 word consists of M-1 pulse intervals between each pulse of a series of M pulses, and is determined by the length of the pulse interval. A receiving circuit for a remote control control signal consisting of M-1 bits encoded with "1" bits, in order to repeatedly transmit this one word remote control control signal multiple times,
To distinguish between each word consisting of M-1 bits transmitted multiple times, the interval between the first pulse of the previous node and the first pulse of the word following this word is greater than or equal to a predetermined time interval. In a remote control control signal receiving circuit that receives a remote control control signal that is repeatedly transmitted several times at intervals, a noise for detecting noise that occurs between pulses that constitute the remote control control signal is used. noise detection period pulse generation means for generating a detection period gate pulse; a signal receiving circuit for receiving the transmitted remote control control signal; and one input gate receiving the noise detection period gate pulse from the noise detection period pulse generation means. and the output of the signal receiving circuit is connected to the other input gate,
a noise detection gate that detects noise mixed in with the remote control control signal from the signal receiving circuit during the generation of the gate pulse during the noise detection period; and a noise detection gate that is set by the noise detection output signal of the noise detection gate, and Noise-clamping flip-flop for clamping and invalidating the received remote control control signal; and a first noise-clamping flip-flop for setting the noise detection period pulse generating means to an initial state after a predetermined time period of the noise detection period gate pulse has elapsed; a reset means; and a second reset means for resetting the noise gate clamp flip 70 knob and releasing the clamping of the signal reception circuit after a predetermined period of time has elapsed since the signal reception circuit was clamped. Features a remote control malfunction prevention circuit.