JPS6367792B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a remote control malfunction prevention circuit, specifically, a remote control system that uses infrared rays to switch channels on a television, etc. The present invention relates to a remote control malfunction prevention circuit that prevents malfunctions.

It is very convenient to freely control TV channels etc. remotely using an infrared remote control device, but such remote control devices that use infrared rays are susceptible to infrared noise from fluorescent lights, etc. It may get mixed into the remote control control signal and cause malfunction. In addition, such infrared noise is generated not only from fluorescent lamps, but also from various lighting equipment that has been developed recently, and even from automatic focusing using infrared rays in cameras etc. Infrared signals emitted by these cameras are also detected as noise, which can cause malfunctions.

An object of the present invention is to provide a remote control malfunction prevention circuit that prevents malfunctions caused by the above-mentioned external infrared noise and operates accurately without malfunctions.

Next, before explaining the present invention with reference to illustrated embodiments, an outline of the configuration of a remote control control signal in such an infrared remote control device will be explained.

In a remote control device that uses infrared rays to switch TV channels, for example, one word of the remote control signal consists of seven serial pulses P ₁ to P ₇ as shown in the received remote control control signal in FIG. It consists of 6 pulse intervals between each pulse, and consists of 6 bits coded with "0" and "1" bits determined by the length of the pulse interval. This 1-word remote control signal made up of 6 bits can be used to send out TV channel information, turn up/down the volume, turn mute on/off, turn up/down channels, etc. It constitutes various control signals that perform the following. More specifically, a bit “0” is defined as a bit “0” when the interval between the pulses is 2 ms.
4ms is defined as a bit "1", and on the receiving side, taking into consideration the variation, a bit "0" is determined when the interval between pulses is in the range of 0.1ms to 3.2ms. , when the interval between pulses is in the range of 3.2ms to 6.4ms, it is judged as a bit "1" and processed. The transmitting side is configured to transmit the one-word remote control signal configured in this manner multiple times, for example, five times, and the receiving side receives the remote control control signal transmitted five times in this way. If at least two of them are the same, it is determined as a legitimate signal and remote control is performed. In order to distinguish between each remote control control signal when transmitting a 6-bit remote control control signal five times in this way, the sending side transmits the previous remote control control signal and then For example, 48 ms is set as the time interval for transmitting the next remote control control signal. And on the receiving side, multiple times (for example, 5 times) at 48ms intervals like this
When the transmitted remote control control signals are received, if there is a gap of at least 6.4 ms between each remote control control signal, it is determined that one word of the remote control control signal has ended. The control signal is determined and received one word at a time, and if at least two or more of the words are the same, the remote control control signal is determined to be correct and control is performed.

In a remote control control signal configured in this way, there is a risk that infrared noise from the outside will be superimposed on this signal and cause a malfunction in the receiving device. This is the case when noise occurs between the two. Therefore, in the present invention, in order to detect the external infrared noise generated in this way, as described in detail below using the drawings, in order to detect the infrared noise generated between the individual pulses, A noise detection period pulse is generated between these individual pulses, and noise is detected by this, and if noise is detected, the remote control control signal received after that is invalidated. . Note that the remote control malfunction prevention circuit of the present invention relays and outputs pulses equivalent to the received pulses if the received series of pulses does not contain noise, and this relay output is separately prepared. What is necessary is to guide the reception confirmation circuit multiple times.

The remote control malfunction prevention circuit of the present invention shown in FIG. It is designed to be input as a received signal to terminal _T1 . The remote control control signal input to this input terminal _T1 is processed through a NAND circuit (hereinafter referred to as
Signal gate 2 consisting of a NAND circuit (abbreviated as NAND circuit)
This signal is supplied to one input terminal of gate 2.
The output of the transistor Tr is supplied to the base of the transistor Tr via the resistor _P1 , and is supplied from the collector of the transistor Tr to the remote control signal receiving device via the output terminal _T2 . In this case, the output waveform of the remote control control signal output from this output terminal T ₂ and the above input terminal T ₁
The waveform is the same as that of the remote control control signal input to the . Also, the output of the signal gate 2 is
The noise detection gate 8 is supplied to one input of the noise detection gate 8 composed of a NAND circuit.
The output of is one of the NAND circuits 5 and 6 that constitute the flip-flop for the noise gate clamp.
It is supplied to one input of circuit 5, thereby setting a flip-flop for noise gate clamping. The output of the NAND circuit 6 of this flip-flop for noise gate clamping is connected to the other input terminal of the signal gate 2, and when this flip-flop for noise gate clamping is set due to the occurrence of noise, the signal gate is set. 2 is suppressed to clamp the output of gate 2. Also, at the bottom right of this circuit are NAND circuits 15 and 16 and a resistor.
A clock oscillation circuit 19 is provided which is composed of R ₅ , R ₆ , a variable resistor VR, and a _capacitor C ₀ .
A clock signal with a clock frequency of 20 KHz and a period of 50 μs is generated by a variable resistor VR and a capacitor _C0 . And this clock oscillation circuit 19
The clock signal output from the NAND circuit 15 is
At the same time, it is supplied to one input terminal of the timing generation control gate 9 composed of a NAND circuit.
It is also supplied to one input terminal of a clock gate 13 composed of a NAND circuit.
3 is supplied to the clock input terminal CL of the timing generation circuit 20 via the NAND circuit 14. This timing generation circuit 20 is made using, for example, a μPD4040C integrated circuit manufactured by NEC Corporation, and is composed of a binary counter that counts the clock signal supplied to the clock input terminal CL mentioned above. . Then, the output of the counted result is output to the output terminal.
Generated as a noise detection period pulse from Q ₅ ,
A reset pulse is generated after 1.6 ms from output terminal Q ₆ , and various pulses are generated as a reset pulse after 12.8 ms from output terminal Q ₉ . Note that this timing generation circuit 20 is configured to operate with the terminal V _SS connected to ground and the terminal V _DD connected to plus 12V.
The output terminal _Q5 of the timing generation circuit 20 is connected to the other input terminal of the gate detection gate 8, and the noise detection period pulse is supplied to the other input gate of the noise detection gate 8. There is. Further, the generation means _Q6 of the timing generation circuit 20 is connected to one input terminal of the NAND circuit 7, and the output of the NAND circuit 6 constituting the flip-flop for the noise gate clamp is connected to the other input of the NAND circuit 7. supply is becoming available. The output of NAND circuit 7 is NAND
Reset timing selection gate 1 consisting of circuit 1
is connected to one input terminal of the reset timing selection gate, and the other input terminal of this reset timing selection gate is connected to the output terminal _Q9 of the timing generation circuit 20.
A reset pulse is supplied via the NAND circuit 4 after 12.8 ms. The output of the reset timing selection gate 1 is connected to the reset terminal RS of the timing generation circuit 20 via a resistor _R4 , and is also connected via the NAND circuit 3 to one of the NAND circuits 6 constituting the flip-flop for noise gate clamping. It is connected to the input terminal and is also supplied to one input terminal of the NAND circuit 10, one of the NAND circuits 10 and 12 constituting the flip-flop for the clock gate. Configuring the flip-flop for the above clock gate
One input of the NAND circuit 12 is connected to the output of the timing generation control gate 9.
The output of the signal gate 2 is connected to the other input of the timing generation control gate 9. Further, the output of the NAND circuit 12 constituting the flip-flop for the clock gate is connected to the other input of the clock gate 13. The reset terminal RS of the timing generation circuit 20 is grounded via a capacitor _C1 , and when the power is turned on, the reset terminal RS is grounded via this capacitor _C1 , and the timing generation circuit 20 is reset. It is becoming more and more like this. Further, the input terminal _T1 is connected to +12V via a resistor _R1 , the base of the transistor Tr is grounded via a resistor _R2 , and the collector is connected to +12V via a resistor _R3 .
Connected to 2V.

The remote control malfunction prevention circuit of the present invention is configured as described above. Next, its operation will be explained with reference to FIGS. 2 and 3.

First, a normal case where there is no noise in the remote control control signal sent as an infrared signal will be described. In this case, the remote control control signal received at the input terminal T ₁ has one word of six pulses P ₁ , P ₂ , P ₃ , P ₄ as shown in the received remote control control signal in FIG. _{. _ _} The width of each pulse is 0.5ms, and when the interval between pulses is 2ms, the bit is "0".
When the interval between pulses is 4 ms, it is identified as bit “1”, and in this case, as shown in the figure, the information represented by this one word remote control control signal is the number of receptions “010100”. It's summery. The one-word remote control control signal configured in this way is sent out repeatedly five times. In this case, the distance between one remote control control signal and the next one is as shown in the figure.
The configuration is such that the interval between the last pulse of this remote control control signal and the first pulse of the next remote control control signal is at least 24 ms with an interval of 48 ms. Considering fluctuations, if the interval between pulses is between 0.1 ms and 3.2 ms, it is judged as a bit "0", and when it is between 3.2 ms and 6.4 ms, it is judged as a bit "1". If the interval between each word of remote control control signal and the next remote control control signal is 6.4 ms or more, it is determined that the previous word of remote control control signal has ended.

Such a remote control control signal is repeated five times and input to the input terminal _T1 of the remote control malfunction prevention circuit shown in Figure 1, but first, before the signal enters the remote control malfunction prevention circuit, the To explain the initial state of the circuit, as a result of the processing performed before that, the output of the NAND circuit 5 constituting the flip-flop for the noise gate clamp is in the "0" state, and the output of the other NAND circuit 5 is in the "0" state.
The output of circuit 6 is in the "1" state. Also, one of the flip-flops for the clock gate is
The output of the NAND circuit 10 is in the "1" state,
The other NAND circuit 12 is in the "0" state.
The timing generation circuit 20 is naturally in a reset state. The clock oscillator circuit 19 always generates a clock signal from the output of the NAND circuit 15, and this output clock signal is generated by the NAND circuit 1 of the flip-flop for the clock gate.
Since the clock gate 13 is inhibited by the output of 2, the signal is not transmitted to the timing oscillation circuit 20 via the NAND circuit 14 beyond this point. Also, the clock signal supplied to the timing generation control gate 9 is prohibited by the "0" signal of the signal gate 2 supplied to the other timing generation control gate 9, and is not supplied to the clock gate flip-flop. It's becoming like that. Note that the signal gate 2 is supposed to be supplied with a remote control control signal through one of its input terminals, _T1 , but if this remote control control signal does not arrive, this input signal is input as shown in the figure. The terminal is in the "1" state, and the other input terminal of this signal gate 2 constitutes a flip-flop for noise gate clamping.
Since the "1" output of the NAND circuit 6 is supplied, the output terminal of the signal gate 2 is in the "0" state.

As mentioned above, in the initial state, first the input terminal
When a remote control control signal comes in via _T1 ,
The signal gate ₂ is actuated by the first pulse P2, and its output becomes "1". As a result, the "1" output of the signal gate 2 is supplied to the signal receiving circuit from the output terminal _T2 via the transistor Tr, and at the same time, this signal is supplied to the other input terminal of the timing generation control gate 9. This gate opens due to the "1" output of the signal gate 2, and the output clock signal of the clock oscillation circuit 19 sets the flip-flop for the clock gate via the timing generation control gate 9, and the output of the NAND circuit 12 is set. Set from “0” to “1” state. As a result, the clock gate 13 becomes gated, and the clock signal of the clock oscillator circuit 19 supplied to one terminal of this clock gate passes through this clock gate 13 and further.
Timing generation circuit 2 via NAND circuit 14
The timing generating circuit 20 supplied to the zero clock input terminal CL is activated to count the supplied clock signal. As a result, this timing generating circuit 20 generates a noise detection period pulse as shown in FIG. 2 from its output terminal _Q5 , and supplies this to the other input terminal of the noise detection gate 8. As can be seen from FIG. 2, the noise detection period pulse generated from the output terminal _Q5 of the timing generation circuit 20 is generated between the pulses of the input remote control control signal. As mentioned above, the external infrared noise generated between the pulses is detected. First, as explained in this example, if there is no noise, the signal gate 2 will not become "1" during this noise detection period pulse due to this noise, so the output of the noise detection gate 8 will be "1"
This leaves us with the state of the output of
The noise gate clamp flip-flop composed of NAND circuits 5 and 6 is designed so that it is never set. Therefore, the NAND that constitutes the flip-flop for this noise gate clamp
Since the output of the circuit 6 does not become "0", the signal gate 2 is thereby inhibited from clamping the received remote control control signal. Further, when the noise detection period pulse generated from the output terminal _Q5 of the timing generation circuit 20 ends, 1.6 ms starts from the next output terminal _Q6 .
After the reset pulse is generated as shown in FIG. 2, the output of the NAND circuit 7 becomes "0".
Then, the “0” output signal of this NAND circuit 7 becomes
It is supplied to one gate of the NAND circuit 10 of the clock gate flip-flop via NAND circuits 1 and 3 to reset the clock gate flip-flop. When the clock gate flip-flop is reset, its NAND circuit 1
The clock gate is inhibited by the output of 2, and the clock signal from the clock oscillation circuit 19 is no longer supplied to the timing generation circuit 20. On the other hand, the “0” output signal of the NAND circuit 7 is
It is supplied to the reset terminal RS of the timing generation circuit 20 via the reset timing selection gate 1,
The timing generating circuit 20 is reset to stop its counting operation. In this way, when one pulse _P1 of the remote control control signal comes, the clock gate flip-flop is activated and the timing generation circuit is activated, and when the predetermined operation is completed, the timing generation circuit 2 is activated.
0 is activated and its predetermined operation is completed, a reset pulse generated from the timing generation circuit 20 terminates this series of operations. This operation is repeated every time one pulse arrives, and it is detected whether or not there is noise between each pulse by the noise detection period pulse generated from the output terminal _Q5 of the timing generation circuit 20 mentioned above. This is what is being detected.

The above is the case where there is no external infrared noise.
Next, the operation will be described in the case where external infrared noise is mixed with the received remote control control signal. This is the pulse of the received remote control control signal, as shown in the timing chart in Figure 3.
P is shown as a noise pulse next to _P2 . In FIG. 3, when the first pulse _P1 of the remote control control signal is input, the operation is the same as that described in FIG. 2 above. Then, when the second pulse P ₂ comes in, the first operation in this circuit until the noise comes is that the pulse P ₂ controls the signal gate 2 and the timing. The clock gate flip-flop is set through the generation control gate 9, which causes the timing operation of the timing generation circuit 20, and the process is the same until the noise detection period pulse is generated from its output terminal _Q5 . . Then, when this noise detection period generation pulse is generated and supplied to the other input terminal of the noise detection gate 8, while this noise detection period pulse is being supplied,
Since the noise pulse is generated, the signal gate 2 momentarily becomes "1", and this signal is detected by the noise detection gate 8, which triggers the noise gate clamp flip-flop. set, the NAND circuit 5
becomes “1” and NAND circuit 6 becomes “0”
becomes the state of When the noise gate clamp flip-flop is set and the output of its NAND circuit 6 becomes "0", the signal gate 2 is inhibited by this "0" output, thereby clamping this circuit. , the remote control control signal coming into the input terminal _T1 is not transmitted to the reception control circuit via the transistor Tr. Furthermore, when the NAND circuit 6 becomes “0”, the NAND circuit 7 becomes inhibited, and the output terminal Q ₆ of the timing generation circuit 20
A reset pulse from the gate is supplied to the clock gate flip-flop and the noise gate clamp flip-flop to prevent each flip-flop from being reset. This noise gate clamp flip-flop is set, and this clamp state is maintained for a predetermined period of time.
After 12.8ms, the above timing generation circuit 2
A 12.8ms reset pulse is generated from output terminal _Q9 of NAND circuit 4,
1 and 3, the noise gate clamp flip-flop and clock gate flip-flop are reset to their initial states. Furthermore, when the reset pulse is generated from the output terminal _Q9 of the timing generation circuit 20 after the above 12.8ms, this signal is supplied to the above-mentioned reset terminal RS via the NAND circuits 4 and 1, so that the timing generation circuit 20 is reset. It's getting old. As described above, once the noise gate clamp flip-flop is set and the signal gate 2 is clamped by this, the subsequent received remote control control signals are disabled until the reset pulse is generated after 12.8ms as described above. The signal is erased and is not transmitted from the output terminal _T2 to the signal reception control circuit via the transistor Tr. As a result, in the signal reception control circuit, the remote control control signal mixed with noise is judged to be incomplete because the number of pulses, that is, the number of bits is insufficient. In the above description, the output terminal of the timing generation circuit 20
The reset pulse after 12.8 ms generated from Q ₉ is one of the pulses due to the circuit configuration of the binary counting circuit that makes up this timing generation circuit 20.
12.8ms, and as mentioned earlier, the same mechanism can be achieved if the interval between one word and the reset control signal is at least 6.4ms, which is the minimum condition. What this means is that, as mentioned above, the interval between pulses is
This comes from the fact that one word is considered to end when it lasts for 6.4ms or more, and as mentioned above, when noise occurs, a clamping operation occurs and the received signal is clamped. Therefore, each pulse of the remote control control signal is not transmitted to the signal receiving circuit via the transistor Tr, thereby notifying the end of one word,
This prevents signals containing noise from being received.

As explained above, according to the present invention, the noise detection period pulse generating means is comprised of the timing generation circuit 20, and the noise is detected by the noise detection period pulse and the circuit is clamped thereby. Since each pulse of the received remote control control signal is not transmitted to the next stage signal reception control circuit and the end of one word is notified, noise generated from external infrared rays in the received remote control control signal is prevented. Even if the remote control signal is mixed in with the noise, this noisy remote control control signal is transmitted to the next signal receiving circuit to prevent malfunction. If there is no noise within the detection period and no noise is detected, the noise detection period pulse generation circuit is reset at the end of the noise detection period so as to immediately return to the noise detection preparation state. If there is noise within the noise detection period, the noise detection period pulse generation circuit is reset when the gate clamp ends.

By selectively using the above two reset periods with and without noise, there is an effect that more accurate noise detection can be performed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a remote control malfunction prevention circuit showing one embodiment of the present invention, and FIGS.
This is a timing chart of the remote control malfunction prevention circuit shown in the figure. 2... Signal gate (signal receiving circuit), 5, 6...
...NAND circuit (flip-flop for noise gate clamp), 8...Noise detection gate, 20...
...Timing generation circuit.

Claims (1)

[Claims] 1. One word is composed of M-1 pulse intervals between each pulse of M pulses in series, and "0", which is determined by the length of the pulse interval,
This is a receiving circuit for a remote control control signal consisting of M-1 bits coded with "1" bit, and in order to repeatedly transmit this one word remote control control signal multiple times, the M-1 bit is transmitted multiple times. A remote control control signal that is repeatedly transmitted multiple times with a predetermined time interval or more between the last pulse of the previous word and the first pulse of the word following this word in order to distinguish between each word. In a remote control control signal receiving circuit that receives a remote control signal, a nozzle detection device generates a gate pulse for a noise detection period every time each pulse occurs in order to detect noise occurring between pulses constituting the remote control control signal. a period pulse generating means; a signal receiving circuit that receives the transmitted remote control control signal; one input gate receives the noise detection period gate pulse from the noise detection period pulse generation means; the other input gate receives the above signal; a noise detection gate to which the output of the reception circuit is connected and which detects noise mixed in with the remote control control signal from the signal reception circuit during the generation of the gate pulse during the noise detection period; and noise of the noise detection gate. a noise gate clamp flip-flop which is set by the detection output signal and clamps the signal receiving circuit to invalidate the received remote control control signal; and noise detection period pulse generating means after a predetermined time period of the noise detection period gate pulse has elapsed. a first reset means for setting the signal to an initial state; and a second reset means for resetting the noise gate clamp flip-flop to release the clamp of the signal receiving circuit after a predetermined time has elapsed since the signal receiving circuit was clamped. A remote control malfunction prevention circuit characterized by having: