JPS595741A - Digital to analog converter - Google Patents
Digital to analog converterInfo
- Publication number
- JPS595741A JPS595741A JP11378482A JP11378482A JPS595741A JP S595741 A JPS595741 A JP S595741A JP 11378482 A JP11378482 A JP 11378482A JP 11378482 A JP11378482 A JP 11378482A JP S595741 A JPS595741 A JP S595741A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- terminal
- output
- diode
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
+11 発明の技術分野
本発明は簡易な構成で実現できるディジタルアナログ変
換器に関する。Detailed Description of the Invention +11 Technical Field of the Invention The present invention relates to a digital-to-analog converter that can be realized with a simple configuration.
121 従来技術と問題点
従来のディジタル・アナログ変換器は第1図に示す構成
例があって複雑であった。すなわちディジタル(1号と
してのシリアルな入カバルスンアップダクンカウンタO
NT Kより計数し、その出力端子へ乃至Q、に対応す
るスイッチSWO乃至5w3Y出力“o”“l”により
開閉すると、例えば電圧Vll−VLの値が抵抗分割さ
れ″′C端子OUTにアナレグ出力v1を得る。このア
ナログ出力V、は離散的であって、ステップmヶ小とす
る罠はハードウェアを大規模にする必要がある。121 Prior Art and Problems The conventional digital-to-analog converter had a complicated configuration as shown in FIG. That is, a digital (serial input up-down counter as No. 1)
When counting from NT K and opening/closing the switches SWO to 5w3Y outputs "o" and "l" corresponding to the output terminals and Q, the value of voltage Vll-VL is divided by resistance and output as an analog signal to terminal C OUT. v1 is obtained. This analog output V, is discrete, and the trap of making the step m small requires a large-scale hardware.
■ 発明の目的
本発明の目的は比較的簡易な構成の回路で且つステップ
幅を小さくアナログ′JIK変換できるディジタル・ア
ナログ変換器を提供すること罠ある。(2) Purpose of the Invention An object of the present invention is to provide a digital-to-analog converter that is capable of analog JIK conversion with a relatively simple circuit configuration and a small step width.
141 発明の構成
前述の目的を達成するための本発明の構成は、抵抗素子
のm−と*j@間にダイオードを介して印加されるティ
ジタル信号Y該抵抗素子の他端と接地間に接続したコン
デンサに印加することによりコンデンサの両端の電圧t
アナログ出方とすることである。141 Structure of the Invention The structure of the present invention to achieve the above-mentioned object is that a digital signal Y applied via a diode between m- and *j@ of a resistance element is connected between the other end of the resistance element and ground. By applying voltage to the capacitor, the voltage t across the capacitor is
The idea is to use an analog method.
(5! 発明の実施例
第21は本発明の一実施例を示す4s成図であって、端
子A、Bはディジタル4g号の人カ端子を示し、入力の
ないとき端子Aは“L”に保持され、“H”レベルの入
力信号が印加される。−万端子Bは入力のないとぎ“H
′″に保持され“°L”レベルの人力が印加される。D
l、D2はダイオードで図示の導通方向に接続され、R
は抵抗素子で、ダイオード側の一端と接地間に前述のデ
ィジタル46号が印加される。Cはコンデンサで抵抗素
子の他洩と接地間に接続され、その両端の電圧がアナロ
グ出力v1となる。端子A4“H”レベルとするパルス
入力のとぎダイオードD1を通してコンデンサa’4光
犠し、出力端すvaの出力は大になる。−万端子Bg“
L”レベルとするパルス入力のとぎダイオードD2Y通
してコンデンサCは放電する。そのとぎコンテンサC馨
光′亀・放電する繰返し数即ちディジタル15号による
制御に応じて出力V、は変化するので簡単な変換器が得
られる。そし′CRとCの定数の適宜な選定によりステ
ップ幅の小さな出力V、Y得ることができる。(5! Embodiment 21 of the invention is a 4S diagram showing an embodiment of the invention, in which terminals A and B represent digital 4G human power terminals, and when there is no input, terminal A is "L". is held at "H" level and an input signal of "H" level is applied.
''' and human power at the level "°L" is applied.D
l, D2 are connected with diodes in the conduction direction shown, and R
is a resistive element, and the above-mentioned digital signal No. 46 is applied between one end on the diode side and ground. C is a capacitor connected between the leak of the resistive element and the ground, and the voltage across the capacitor becomes the analog output v1. When the pulse input to the terminal A4 is set to "H" level, the capacitor a'4 passes through the diode D1, and the output from the output terminal va becomes large. -Multiple terminal Bg“
The capacitor C is discharged through the switching diode D2Y of the pulse input which is set to L" level.The output V changes according to the number of repetitions of the switching capacitor C, that is, the control by digital No. 15, so it is easy to A converter is obtained. By appropriately selecting the constants of 'CR and C, outputs V and Y with small step widths can be obtained.
m3図f!第2図に示す回ruンパルス信号の歪除去回
路に応用した回路例χ示している。INは歪をもったパ
ルス信号列の入力端子、DTは歪検出制御回路で出力端
子ム、Bを第2図の入力端子ム、Bと対応させる。通常
は端子A4“L”、端子BY“R”レベルとしておく。m3 figure f! A circuit example χ shown in FIG. 2 is applied to the distortion removal circuit for the run pulse signal. IN corresponds to an input terminal for a pulse signal train having distortion, DT corresponds to an output terminal of a distortion detection control circuit, and B corresponds to an input terminal B in FIG. Normally, terminal A4 is set to "L" level and terminal BY is set to "R" level.
そして端子INにパルス入力がありて歪があるとぎ歪検
出制御回路DTの端子ムに“H″を出力させ、ないとき
端子Bに“L″ン出力せる。そのため信号入力に歪があ
るとコンデンサCは抵抗R4介して充電されコンデンサ
Cの両端の電位は高くなる。When there is a pulse input to the terminal IN and there is distortion, the distortion detection control circuit DT outputs "H" to the terminal, and when there is no distortion, it outputs "L" to the terminal B. Therefore, when there is distortion in the signal input, the capacitor C is charged through the resistor R4, and the potential across the capacitor C becomes high.
その電位が加算器2に帰還され入力信号に対し歪ケ小に
する方向で重畳される。歪がなくなったときコンデンサ
Cの電位は低下し、次に発生した歪においてCの電位を
再び上昇させる。歪検出の周期と比較し十分太ぎな時足
数の抵抗素子・コンデンサを形成すると、入力信号は歪
を除去され綺麗な出力信号NH3得ることができる。The potential is fed back to the adder 2 and superimposed on the input signal in a direction that reduces distortion. When the distortion disappears, the potential of the capacitor C decreases, and the potential of the capacitor C is raised again when the next distortion occurs. By forming a number of resistive elements and capacitors that are sufficiently thick compared to the period of distortion detection, distortion can be removed from the input signal and a clean output signal NH3 can be obtained.
+61 発明の効果
このようにして本発明によると簡単な構成であってもス
テップ幅の小さいディンタル・アナログ変換器ン得るこ
とができる。+61 Effects of the Invention In this way, according to the present invention, a digital-to-analog converter with a small step width can be obtained even with a simple configuration.
第1図は従来のディジタル・7ナログ変換器器の構成例
を示す図、
第2図は本発明の一実施例の栖゛成馨示す図、第3図は
第2図の具体的応用例を示す図である。
R・・・・・・抵抗素子 C・・・・・・コンデンサ
D1.D2・・・・・・ダイオード
DT・・・・−・歪検出制御回路
%軒出願人冨士通株式会社
代理人弁理士 鈴木栄祐
2Fig. 1 is a diagram showing a configuration example of a conventional digital/7-analog converter, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, and Fig. 3 is a specific application example of Fig. 2. FIG. R...Resistance element C...Capacitor D1. D2...Diode DT...--Distortion detection control circuit% Applicant: Fujitsu Co., Ltd. Representative Patent Attorney Eisuke Suzuki 2
Claims (1)
るディジタル信号を該抵抗素子の他端と接地間に接続し
たコンデンサに印加することによりコンデンサの両端の
電圧ンアナログ出力とすることを特徴とするディジタル
・アナログ変換器。A digital signal applied between one end of the resistive element and ground via a diode is applied to a capacitor connected between the other end of the resistive element and ground, thereby producing an analog output of the voltage across the capacitor. Digital to analog converter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11378482A JPS595741A (en) | 1982-06-30 | 1982-06-30 | Digital to analog converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11378482A JPS595741A (en) | 1982-06-30 | 1982-06-30 | Digital to analog converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS595741A true JPS595741A (en) | 1984-01-12 |
Family
ID=14621009
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11378482A Pending JPS595741A (en) | 1982-06-30 | 1982-06-30 | Digital to analog converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS595741A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61169024A (en) * | 1985-01-21 | 1986-07-30 | Fujitsu Ltd | Analog output processing system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4839856A (en) * | 1971-09-23 | 1973-06-12 | ||
JPS5420649A (en) * | 1977-07-15 | 1979-02-16 | Matsushita Electric Works Ltd | Digital-to-analog converter circuit |
JPS5432520U (en) * | 1977-08-04 | 1979-03-03 |
-
1982
- 1982-06-30 JP JP11378482A patent/JPS595741A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4839856A (en) * | 1971-09-23 | 1973-06-12 | ||
JPS5420649A (en) * | 1977-07-15 | 1979-02-16 | Matsushita Electric Works Ltd | Digital-to-analog converter circuit |
JPS5432520U (en) * | 1977-08-04 | 1979-03-03 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61169024A (en) * | 1985-01-21 | 1986-07-30 | Fujitsu Ltd | Analog output processing system |
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