JP6405149B2 - D / A converter circuit - Google Patents

Description

  The present invention relates to a D / A conversion circuit that converts digital data into an analog signal.

  FIG. 6A shows a PWM (Pulse Width Modulation) signal used in a conventional D / A conversion circuit, and FIG. 6B shows a pulse division PWM signal. 6A and 6B, the vertical axis represents voltage, and the horizontal axis represents time. In order to respond at high speed, the pulse division PWM signal divides the PWM pulse period (four divisions in the example of FIG. 6B) to increase the frequency of the modulation signal. By increasing the frequency of the modulation signal, the time constant of the analog filter used in the D / A conversion circuit can be decreased under the same ripple condition as the PWM signal. Although the response speed of the D / A converter circuit can be increased by lowering the filter time constant, there is a limit to the method of increasing the response speed by lowering the filter time constant. The conversion accuracy of the / A conversion circuit may deteriorate.

  FIG. 7 is a block diagram showing the configuration of a conventional D / A conversion circuit that converts digital data into an analog signal using a pulse division PWM signal, and FIG. 8 is a block diagram showing the configuration of another D / A conversion circuit. The configuration of FIG. 7 is disclosed in Patent Document 1, and the configuration of FIG. 8 is disclosed in Patent Document 2. The D / A conversion circuit in FIG. 7 includes a PWM signal generation unit 100, a fraction processing unit 101, and a smoothing unit 102. The PWM signal generation unit 100 is applied with the main clock MCLK and the higher-order bits of the setting data DSET, generates a PWM signal and a PWM cycle signal, and outputs these signals to the fraction processing unit 101. The fraction processing unit 101 receives the main clock MCLK and the lower-order bits of the setting data DSET, generates a divided PWM signal, and outputs this signal to the smoothing unit 102. The smoothing unit 102 smoothes the divided PWM signal and outputs an analog signal.

  The D / A conversion circuit in FIG. 8 includes a PWM circuit 200, a superimposing unit 201, and a low-pass filter 202. The PWM circuit 200 generates a pulse width modulated pulse P (X) that is pulse width modulated based on the upper N bits X of the digital input value Din. The superimposing unit 201 applies the unit pulse U corresponding to one clock of the number corresponding to the lower m bits Z of the digital input value Din to the last one clock of the conversion cycle T corresponding to the upper N bits of the digital input value Din. Disperse and superimpose. If the time for one clock is t, the conversion cycle T can be given by 2N × t. The low-pass filter 202 removes the carrier frequency ripple of the PWM circuit 200 from the output of the superimposing unit 201 and outputs an analog output value Aout. The PWM circuit 200 includes a conversion value register 203, comparators 204 and 205, and an N-bit counter 206. The superimposing unit 201 includes an m bit rate multiplier 207, an AND circuit 208, and an OR circuit 209.

Each of the D / A conversion circuits in FIGS. 7 and 8 divides the PWM signal by dividing the setting data into upper bits and lower bits.
FIG. 9 is a block diagram showing the configuration of another conventional D / A conversion circuit. The D / A conversion circuit of FIG. 9 uses an ASIC (Application Specific Integrated Circuit) 300 to improve responsiveness. When the digital data for generating the PWM signal changes, the response is improved by switching to an analog filter composed of a resistor 302 and a capacitor 303 with a small time constant. When there is no change in the digital data, the output ripple is suppressed by switching to an analog filter comprising a resistor 301 and a capacitor 303 with a large time constant.

JP 2002-353814 A JP 2010-278669 A JP 2003-101413 A

  In a D / A conversion circuit used for a temperature sensor or a pressure sensor, when an input change is large, it is required to be stabilized to a highly accurate output value (> 15 bits) and to a certain value (for example, 63.2). % Response), a high-speed response is required. In order to satisfy the two requirements of high accuracy and high speed response, a mechanism is required that can change the time constant of the D / A conversion filter according to the state of the input signal. A configuration as shown in FIG. 9 has been proposed as a D / A conversion circuit capable of varying the time constant of the filter.

However, in the D / A conversion circuit shown in FIG. 9, it is necessary to provide two output terminals of the IC and two resistors outside the IC in order to change the time constant of the filter. There was a problem that would increase.
Furthermore, in the D / A conversion circuit shown in FIG. 9, when a high-order filter is provided, it is necessary to provide a control terminal from the IC and an external element such as a switch, which increases circuit area and cost. There was a problem of doing.

The present invention has been made to solve the above-described problem, and can switch the time constant of the smoothing filter used for the output of the D / A conversion circuit at a lower cost and with a smaller circuit area than in the prior art. It is an object to provide a D / A conversion circuit.
Another object of the present invention is to provide a D / A conversion circuit that can reduce the circuit area and cost even when a high-order filter is provided as a smoothing filter used for the output of the D / A conversion circuit. And

The D / A conversion circuit of the present invention has a modulation circuit that outputs a modulation signal having a duty ratio corresponding to the value of digital data, and a first time constant when no control signal is input, and the control signal is input A time constant switching function for setting a second time constant smaller than the first time constant, a low-pass filter for smoothing the modulation signal and outputting an analog signal, and detecting a change in the digital data A change detection circuit that outputs the control signal for a certain period of time, the change detection circuit delays the digital data by one sampling period, and outputs the output data of the delay circuit from the digital data. A subtracting circuit for subtracting; an absolute value circuit for obtaining an absolute value of output data of the subtracting circuit; a register capable of setting a threshold; and an output value of the absolute value circuit Said control signal fixed time output when it exceeds the threshold set for the register, the output value of the absolute value circuit is composed of a comparator does not output the control signal when below the threshold value, The modulation circuit, at least a part of the low-pass filter, and the change detection circuit are provided in an integrated circuit, and the time constant of the low-pass filter is in the state of the second time constant for the predetermined time. The analog signal that changes according to digital data is set to a time when the analog signal changes to 63.2% of the final value .
Further, in one configuration example of the D / A conversion circuit of the present invention, the low-pass filter includes a first and a second inserted in series between an output terminal of the modulation circuit and an output terminal of the D / A conversion circuit. A switch for short-circuiting the second resistor when the control signal is input, and a capacitor provided as an external element of the integrated circuit between the output terminal of the D / A conversion circuit and the ground. It is characterized by being configured.

In addition, one configuration example of the D / A conversion circuit of the present invention further includes a buffer circuit connected to the output terminal of the low-pass filter in the integrated circuit, and the low-pass filter includes the output terminal of the modulation circuit. And first and second resistors inserted in series between the input terminal of the buffer circuit, a switch for short-circuiting the second resistor when the control signal is input, and an input of the buffer circuit It is comprised from the capacitor | condenser provided between a terminal and earth | ground.
The D / A conversion circuit according to the present invention further includes a buffer circuit connected to the output terminal of the low-pass filter in the integrated circuit, and the low-pass filter includes a plurality of primary filters. Each of the primary filters includes first and second resistors inserted in series between an output terminal of the modulation circuit and an input terminal of the buffer circuit, and the control circuit. A switch that short-circuits the second resistor when a signal is input; and an external element of the integrated circuit provided between an output-side terminal of the two terminals of the second resistor and the ground It is comprised from a capacitor | condenser.

  According to the present invention, a high-accuracy and high-speed response D / A conversion circuit can be realized by switching the time constant of the low-pass filter in accordance with input digital data. In the present invention, the circuit area and cost can be reduced by providing at least part of the low-pass filter in the integrated circuit.

  In the present invention, in addition to the low-pass filter, the buffer circuit is built in the integrated circuit, so that external components of the integrated circuit can be reduced.

  In the present invention, the low-pass filter has a configuration in which a plurality of stages of primary filters are cascade-connected, and each primary filter is composed of a first resistor, a second resistor, a switch, and a capacitor. Even when a high-order filter is provided, the circuit area and cost can be reduced.

1 is a block diagram showing a configuration of a D / A conversion circuit according to a first embodiment of the present invention. It is a figure which shows the waveform of each part of the D / A converter circuit which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the D / A converter circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the D / A converter circuit which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the D / A converter circuit which concerns on the 4th Embodiment of this invention. It is a figure explaining a PWM signal and a pulse division | segmentation PWM signal. It is a block diagram which shows the structure of the conventional D / A conversion circuit. It is a block diagram which shows the structure of the other conventional D / A conversion circuit. It is a block diagram which shows the structure of the other conventional D / A conversion circuit.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the D / A conversion circuit according to the first embodiment of the present invention. The D / A conversion circuit according to the present embodiment includes a modulation circuit 2, a low-pass filter 3, a delay circuit 4 including a D flip-flop, a subtraction circuit 5, an absolute value circuit 6, a register 7, a comparator 8, Consists of Such a D / A conversion circuit is realized by an integrated circuit (IC) 1. The delay circuit 4, the subtraction circuit 5, the absolute value circuit 6, the register 7, and the comparator 8 constitute a change detection circuit that detects a change in the digital data IN.

  2A to 2E are diagrams showing waveforms of respective parts of the D / A conversion circuit of FIG. Digital data IN shown in FIG. 2A is input to the modulation circuit 2. The modulation circuit 2 outputs a modulation signal (PWM signal or ΔΣ modulation signal) VIN having a duty ratio corresponding to the value of the digital data IN as shown in FIG. In the example of FIG. 2B, the case where the modulation circuit 2 outputs a PWM signal is described.

The low-pass filter 3 smoothes the modulation signal VIN and outputs an analog signal VOUT. The low-pass filter 3 is an active filter that can change the time constant inside the IC 1.
The delay circuit 4 composed of a D flip-flop delays the digital data IN by one sampling period.

The subtraction circuit 5 subtracts the output data of the delay circuit 4 from the digital data IN. As a result, the difference between the digital data IN and the digital data IN one sampling period before is obtained.
The absolute value circuit 6 obtains the absolute value of the output data of the subtracting circuit 5. A threshold value THRES is set in the register 7 in advance.

  The comparator 8 compares the output value of the absolute value circuit 6 with the threshold value THRES set in the register 7. The comparator 8 is a control signal for reducing the time constant of the low-pass filter 3 as shown in FIG. 2 (E) when the output value of the absolute value circuit 6 exceeds the threshold value THRES, that is, when the digital data IN changes. ACT is output for a certain time, and when the output value of the absolute value circuit 6 is not more than the threshold value THRES, that is, when the digital data IN does not change, the control signal ACT is not output.

  When the digital data IN changes as shown in FIG. 2A and the time constant of the low-pass filter 3 is large, the ripple of the analog signal VOUT is suppressed as shown by the characteristic 40 in FIG. However, the response to the digital data IN is deteriorated. When the time constant of the low-pass filter 3 is small, the response is good as shown by the characteristic 41 in FIG. 2C, but the ripple of the analog signal VOUT is large, and the conversion accuracy of the D / A converter circuit is set to a predetermined value. It may not be possible to keep the range.

  On the other hand, in the present embodiment, as described above, the time constant of the low-pass filter 3 is reduced only for a certain time T1 after the digital data IN changes, and the digital data IN does not change or is constant. When the time T1 has elapsed, the time constant of the low-pass filter 3 is increased. Thus, in this embodiment, as illustrated in FIG. 2D, the response to the digital data IN can be improved while suppressing the ripple of the analog signal VOUT to a predetermined accuracy.

The fixed time T1 needs to be set in advance so that the analog signal VOUT does not overshoot. Specifically, for example, the time during which the analog signal VOUT changes to 63.2% when the time constant of the low-pass filter 3 is small may be set as the fixed time T1.
The threshold value THRES is determined according to the application, but the threshold value THRES set in the register 7 can be changed by an external input.

  Thus, in this embodiment, a D / A conversion circuit with high accuracy and high speed response can be realized. In the present embodiment, since the low pass filter 3 is built in the IC 1, the number of output terminals of the IC 1 can be reduced to one, so that the number of terminals and external elements can be reduced, and the circuit area and cost are reduced. be able to.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration of a D / A conversion circuit according to the second embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIG. This embodiment shows a specific example of the low-pass filter 3 of the first embodiment.

  The low-pass filter 3 according to the present embodiment includes resistors 30 and 31 provided in series between the output terminal of the modulation circuit 2 and the output terminal of the D / A conversion circuit (output terminal of the IC 1), and control from the comparator 8. The switch 32 is configured to short-circuit the resistor 31 according to the signal ACT, and the capacitor 9 is provided as an external element of the IC 1 between the output terminal of the D / A conversion circuit and the ground.

  When the control signal ACT is output from the comparator 8, the switch 32 is turned on. Thereby, since the resistor 31 is short-circuited, the time constant of the low-pass filter 3 is reduced. When the control signal ACT is not output, the switch 32 is turned off. Thereby, since the resistors 30 and 31 are connected in series, the time constant of the low-pass filter 3 is increased.

In the conventional D / A conversion circuit shown in FIG. 9, in order to change the time constant of the filter, it is necessary to provide two output terminals of the IC and to provide resistors 301 and 302 and a capacitor 303 outside the IC. .
On the other hand, in the present embodiment, by incorporating the resistors 30 and 31 of the low-pass filter 3 in the IC 1, the output terminal of the IC 1 can be suppressed to one. Also in the present embodiment, the capacitor 9 is required as an external element of the IC1, but the circuit area and cost can be reduced by incorporating the resistors 30 and 31 in the IC1.

  When a primary RC filter is used as the low-pass filter 3 as in the present embodiment, the response time (63.2% response) of the low-pass filter 3 is RC, and the ripple of the analog signal VOUT is (A / 2) × [1-EXP {-T / 2 / (RC)}]. Assuming that the resistance value of the resistor 30 is R1, the resistance value of the resistor 31 is R2, and the capacitance value of the capacitor 9 is C, the RC of the above response time and ripple equation, that is, the time constant RC of the low-pass filter 3, When off, (R1 + R2) × C (first time constant), and when switch 32 is on, R1 × C (second time constant). A is the amplitude of the rectangular wave (modulation signal VIN output from the modulation circuit 2) input to the low-pass filter 3, and T is the period of the rectangular wave.

  When R1 = 10 kΩ, R2 = 90 kΩ, C = 100 nF, modulation signal frequency 100 kHz, 1 V full scale, when the switch 32 is on, the response time of the low-pass filter 3 is 1 ms, and the ripple of the analog signal VOUT is 2.5 mV ( 0.25% FS). When the switch 32 is off, the response time of the low-pass filter 3 is 10 ms, and the ripple of the analog signal VOUT is 0.25 mV (0.025% FS). When the design specification is given with a response time of 1 ms and a ripple of 0.1% FS, the specification can be satisfied by turning on the switch 32 for about 1 ms when the digital data IN changes (that is, T1 = 1 ms). it can.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing a configuration of a D / A conversion circuit according to the third embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIG. This embodiment is characterized in that the buffer circuit 10 provided outside the IC 1 in the first and second embodiments is built in the IC 1. The buffer circuit 10 drives the output of the low pass filter 3.

In the present embodiment, since the buffer circuit 10 is built in the IC 1, the capacitor 33 is provided inside the IC 1 instead of the capacitor 9 which is an external element in the second embodiment.
Thus, in the present embodiment, external parts can be reduced as compared with the first and second embodiments.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of a D / A conversion circuit according to the fourth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. In the present embodiment, a high-order filter is provided as the low-pass filter 3.

  The low-pass filter 3 according to the present embodiment corresponds to the resistors 30a, 31a, 30b, and 31b provided in series between the output terminal of the modulation circuit 2 and the input terminal of the buffer circuit 10 and the control signal ACT from the comparator 8. Switches 32a and 32b for short-circuiting the resistors 31a and 31b, a capacitor 9a provided between the connection point of the resistors 31a and 30b as an external element of IC1 and the ground, and an output terminal of the low-pass filter 3 as an external element of IC1 ( The capacitor 9b is provided between the input terminal of the buffer circuit 10 and the ground.

  The low-pass filter 3 is formed by connecting two stages of primary filters in cascade. The first-stage primary filter includes resistors 30a and 31a, a switch 32a, and a capacitor 9a, and the subsequent-stage primary filter includes resistors 30b and 31b, a switch 32b, and a capacitor 9b.

  When the control signal ACT is output from the comparator 8, the switches 32a and 32b are turned on. As a result, the resistors 31a and 31b are short-circuited, so that the time constant of the low-pass filter 3 is reduced. When the control signal ACT is not output, the switches 32a and 32b are turned off. As a result, the resistors 30a, 31a, 30b, and 31b are connected in series, so that the time constant of the low-pass filter 3 is increased.

In the conventional D / A conversion circuit shown in FIG. 9, in order to provide a high-order filter, it is necessary to provide a control terminal from the IC and an external element such as a switch.
On the other hand, in this embodiment, even when a high-order filter is provided as the low-pass filter 3 by incorporating the resistors 30a, 31a, 30b, and 31b of the low-pass filter 3 and the switches 32a and 32b in the IC 1, Circuit area and cost can be reduced.

In this embodiment, a low-pass filter 3 in which primary filters are cascaded in two stages is used. However, the present invention is not limited to this, and primary filters may be cascaded in three or more stages.
In this embodiment, capacitors 9a and 9b are provided outside IC1, but capacitors 9a and 9b may be provided inside IC1 as in the third embodiment.

  The present invention can be applied to a D / A conversion circuit.

  DESCRIPTION OF SYMBOLS 1 ... Integrated circuit, 2 ... Modulation circuit, 3 ... Low pass filter, 4 ... Delay circuit, 5 ... Subtraction circuit, 6 ... Absolute value circuit, 7 ... Register, 8 ... Comparator, 9, 9a, 9b, 33 ... Capacitor, 10 ... buffer circuit 30, 31, 30a, 31a, 30b, 31b ... resistor, 32, 32a, 32b ... switch.

Claims (4)

A modulation circuit that outputs a modulation signal having a duty ratio according to the value of the digital data;
A time constant switching function for setting a first time constant when no control signal is input, and a second time constant smaller than the first time constant when the control signal is input; A low pass filter that outputs an analog signal by smoothing
A change detection circuit that outputs the control signal for a predetermined time when a change in the digital data is detected;
The change detection circuit includes:
A delay circuit for delaying the digital data by one sampling period;
A subtracting circuit for subtracting the output data of the delay circuit from the digital data;
An absolute value circuit for obtaining an absolute value of output data of the subtracting circuit;
Registers with configurable thresholds;
When the output value of the absolute value circuit exceeds a threshold value set in the register, the control signal is output for a predetermined time, and when the output value of the absolute value circuit is equal to or less than the threshold value, the control signal is output. And a comparator that does not output
The modulation circuit, at least a part of the low-pass filter, and the change detection circuit are provided in an integrated circuit ,
The predetermined time is set to a time when the analog signal that changes according to the digital data changes to 63.2% of the final value in a state where the time constant of the low-pass filter is the second time constant. A D / A conversion circuit characterized by the above. The D / A converter circuit according to claim 1,
The low-pass filter is
First and second resistors inserted in series between the output terminal of the modulation circuit and the output terminal of the D / A conversion circuit;
A switch that short-circuits the second resistor when the control signal is input;
A D / A conversion circuit comprising a capacitor provided as an external element of the integrated circuit between an output terminal of the D / A conversion circuit and ground. The D / A converter circuit according to claim 1,
Furthermore, a buffer circuit connected to the output terminal of the low-pass filter is provided inside the integrated circuit,
The low-pass filter is
First and second resistors inserted in series between the output terminal of the modulation circuit and the input terminal of the buffer circuit;
A switch that short-circuits the second resistor when the control signal is input;
A D / A conversion circuit comprising a capacitor provided between an input terminal of the buffer circuit and ground. The D / A converter circuit according to claim 1,
Furthermore, a buffer circuit connected to the output terminal of the low-pass filter is provided inside the integrated circuit,
The low-pass filter is a cascade connection of a plurality of primary filters.
Each of the first order filters is
First and second resistors inserted in series between the output terminal of the modulation circuit and the input terminal of the buffer circuit;
A switch that short-circuits the second resistor when the control signal is input;
A D / A converter circuit comprising a capacitor provided between an output terminal of the two terminals of the second resistor and a ground as an external element of the integrated circuit.

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