JP5409122B2 - Averaging circuit that outputs the moving average of the input signal - Google Patents

Description

  The present invention relates to an averaging circuit that outputs a moving average of an input signal, and is effective, for example, for efficiently suppressing noise from an input signal in which pulse noise is mixed at random.

  For example, in a sensor system that detects the behavior of a detection target by converting it into a voltage change by a sensor, pulse noise is often superimposed on the output signal (sensor signal) from the sensor, which often hinders detection. . In such a case, in order to appropriately perform detection by the sensor, it is necessary to selectively suppress random pulse noise from the sensor signal.

  As a circuit for suppressing random pulse noise, for example, an averaging circuit described in Japanese Patent Application Laid-Open No. 2000-261513 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2008-66857 (Patent Document 2) is known. .

  In Japanese Patent Laid-Open No. 2000-261513, an analog input signal periodically sampled is digitized (quantized) by an AD converter, and this digitized input signal is held by a flip-flop (memory). It is disclosed that the level of the input signal is averaged by repeatedly adding the next digitized input signal to the digitized input signal.

  Japanese Patent Application Laid-Open No. 2008-66857 discloses a sampling data averaging circuit that samples digitized input data a plurality of times and calculates an average value thereof.

  In these averaging circuits, the analog input signal is sampled and digitized (quantized) and stored in the memory, and the random averaged noise is calculated by calculating the moving average of the sampling data for the latest multiple times. Let it be suppressed.

The above-described conventional averaging circuit requires a pre-processing for once digitizing an input signal that may contain noise in the averaging process for suppressing random pulse noise. It was.
SUMMARY OF THE INVENTION An object of the present invention is to provide an averaging circuit that can perform an averaging process by moving average in the form of an analog signal without digitizing the analog input signal.

The averaging circuit according to the present invention is specified by the following (11) to (15).
(11) Having an operational amplifier in which the non-inverting input is connected to the reference potential and an integrating capacitive element is connected between the output and the inverting input to form an integrating circuit. (12) The integrated output voltage of the operational amplifier is held. (13) An input signal is applied to one electrode terminal, and the other electrode terminal is connected to the reference potential or the integration of the operational amplifier via the first switching circuit or the second switching circuit. (14) One electrode terminal is connected to the integral output of the operational amplifier or the integral input of the operational amplifier via the third switching circuit or the fourth switching circuit. And having the second input capacitance element connected to the reference potential at the other electrode terminal. (15) First and third switches The switching circuit and the second and fourth switching circuits are turned on / off at a frequency sufficiently higher than the frequency range of the input signal, the other is turned on in one off section, and the other is turned on in the other off section. Is turned on

  Without digitizing the analog input signal, it is possible to perform averaging processing by moving average while maintaining the analog signal form. As a result, there can be obtained an advantage that the analog signal processing at the subsequent stage can be easily performed while the circuit is simplified and the power consumption is reduced.

It is a figure which shows the operation | movement timing chart of the averaging circuit which comprises one Embodiment of this invention, and its principal part. It is a waveform which shows the 1st example (step response) of the input-output response characteristic in the averaging circuit based on this invention. It is a waveform which shows the 2nd example (500 Hz sin wave input response) of the input-output response characteristic in the averaging circuit based on this invention. It is a waveform which shows the 3rd example (800Hz sin wave input response) of the input-output response characteristic in the averaging circuit based on this invention. It is a waveform which shows the 4th example (1 KHz sine wave input response) of the input-output response characteristic in the averaging circuit based on this invention. It is a waveform which shows the 5th example (1.5 KHz sine wave input response) of the input-output response characteristic in the averaging circuit based on this invention. It is a waveform which shows the 6th example (2 KHz sine wave input response) of the input-output response characteristic in the averaging circuit based on this invention. It is a waveform which shows the 7th example (5 KHz sine wave input response) of the input-output response characteristic in the averaging circuit based on this invention.

=== Configuration of Circuit ===
FIG. 1 shows an operation timing chart of an averaging circuit and an essential part thereof according to an embodiment of the present invention. Averaging circuit shown in the figure, an operational amplifier (op amp) 12, integrating capacitor Cf, an output capacitor element Co, the first and second input capacitance element C1, C2, first to fourth switching circuits p H1 to ph4, a reset switch SWR, and the like.
In the figure, resistance elements and the like provided in the actual circuit are shown with constants. In addition, each capacitance element Cf, Co, C1, C2 is given a capacitance value in an actual circuit.

  In the operational amplifier 12, the non-inverting input (+) is connected to the reference potential, and the integrating capacitive element Cf is connected between the output and the inverting input (−) to form an integrating circuit. A reset switch SWR is connected in parallel to the integration capacitor element Cf. This switch SWR is for initial setting, and is set to an on state only at the start of the operation, and thereafter is always in an off state.

  The output line of the operational amplifier 12 is connected to an output capacitive element Co that holds the integrated output voltage Vout. The integrated output voltage Vout applied to the output capacitive element Co is supplied to a circuit (not shown) at the subsequent stage as an output voltage of the averaging circuit.

  The input signal Vin of the averaging circuit is taken out from a signal source such as a sensor through the amplifier 11 and applied to one electrode terminal of the first input capacitance element C1. The other electrode terminal of the first input capacitive element C1 is alternately connected to the reference potential or the integration input of the operational amplifier 12 via the first switching circuit ph1 or the second switching circuit ph2.

  The second input capacitive element C2 has one electrode terminal connected to the integral output of the operational amplifier 12 or the integral input of the operational amplifier 12 via the third switching circuit ph3 or the fourth switching circuit ph4. The other electrode terminal is connected to the reference potential.

  The first and third switching circuits ph1 and ph3 and the second and fourth switching circuits ph2 and ph4 have a frequency sufficiently higher than the frequency range of the input signal Vin as shown in the operation timing chart in the drawing. It is turned on / off at ftrf (for example, 20 KHz), the other is turned on in one off section, and the other is turned on in the other off section.

=== Operation of the circuit ===
In FIG. 1, first, a section in which the switching circuits ph1 and ph3 are on and ph2 and ph4 are off is defined as a first phase. Further, a section in which the switching circuits ph1 and ph3 are off and ph2 and ph4 are on is defined as a second phase.

In the first phase, the other electrode terminal of the first input capacitive element C1 is connected to the reference potential via ph1, and one electrode terminal of the second input capacitive element C2 is connected to the integrated output voltage via ph3. Connected to Vout.
In the second phase, the other electrode terminal of the first input capacitive element C1 and one electrode terminal of the second input capacitive element C2 are connected, and this connection point is connected to the inverting input of the operational amplifier 12. . In this second phase, two input capacitive elements C1 and C2 are connected in series, and a voltage appearing at the midpoint of this series connection is applied to the inverting input of the operational amplifier 12.

  If the integrated output voltage Vout is an initial value of zero in the first phase, the input signal (input voltage) Vin is divided by the two input capacitance elements C1 and C2 in the second phase thereafter. The divided voltage is input to the inverting input of the operational amplifier 12 as an integral input voltage. The operational amplifier 1 integrates the integration input voltage with respect to time in the second phase interval. The integrated output voltage Vout is held by the output capacitive element Co and is applied to and charged by the second input capacitive element C2.

  Also in the first phase after the second phase, the input voltage Vin is divided by the two input capacitive elements C1 and C2, but at this time, one input capacitive element C2 is integrated in the immediately preceding first phase. The output voltage Vout is charged in advance.

  Therefore, in this first phase, a voltage obtained by dividing the total value of the current input voltage Vin and the previous integrated output voltage Vout by C1 and C2 is input to the inverting input of the operational amplifier 12 as an integrated input voltage. The operational amplifier 12 time-integrates the integrated input voltage in the second phase interval in the same manner as described above. Then, the integrated output voltage Vout is held in the output capacitive element Co and charged in the second input capacitive element C2.

  As described above, at each transition from the first phase to the second phase, the arithmetic mean value of the current input voltage Vin and the previous integrated output voltage Vout is integrated and output. By repeating such an operation cycle, an averaging process using a moving average is performed. Thereby, random pulse noise can be efficiently suppressed.

  It should be noted here that the above-described averaging process based on the moving average can be performed in the form of the analog signal without digitizing the analog input signal. As a result, there can be obtained an advantage that the analog signal processing at the subsequent stage can be easily performed while the circuit is simplified and the power consumption is reduced.

=== Input / output response characteristics ===
2 to 8 show the input / output response characteristics of the averaging circuit described above.
First, FIG. 2 illustrates a response waveform when the input voltage (input signal) Vin is a square wave. In this case, the frequency Fsig of the input voltage Vin is 500 Hz, and the repetition frequency (conversion frequency) f trf of the first phase and the second phase is 20 KHz which is sufficiently higher than that of the input voltage Vin. The output voltage Vout is updated step by step every time the first phase and the second phase are repeated, and the output waveform thereof is a waveform obtained by subjecting the input voltage Vin to primary low-pass filter processing, as shown in FIG.

3 to 8 each illustrate a response waveform when the input voltage Vin is a sine wave. In each figure, the conversion frequency f trf is 20 KHz, but the frequency Fsig of the input voltage Vin is 500 Hz (FIG. 3), 800 Hz (FIG. 4), 1 KHz (FIG. 5), 1.5 KHz (FIG. 6), It is different from 2 KHz (FIG. 7) and 5 KHz (FIG. 8).

As shown in the figure, a low-pass filter characteristic in which the phase shift and attenuation of the output voltage Vout increase as the frequency of the input voltage Vin increases between the input and output, and the cutoff frequency of the low-pass filter is This is approximately 1/20 of the conversion frequency f trf.

11,12 Operational Amplifier (Op Amp)
Cf integral capacitive element Co output capacitive element C1 first input capacitive element C2 second input capacitive element
p H1～ph4 first to fourth switching circuits SWR reset switch Vout integrated output voltage Vin input signal (voltage)
f trf conversion frequency (on-off cycle of the switching circuit p h1~ph4)
Fsig Input signal (voltage) Vin frequency

Claims (1)

An operational amplifier in which a non-inverting input is connected to a reference potential and an integrating capacitive element is connected between the output and the inverting input to form an integrating circuit;
An output capacitive element that holds the integrated output voltage of the operational amplifier;
An input signal is applied to one of the electrode terminals, and the other electrode terminal is connected to a reference potential or an integration input of the operational amplifier via the first switching circuit or the second switching circuit. Elements,
One electrode terminal is connected to an integration output of the operational amplifier or an integration input of the operational amplifier via a third switching circuit or a fourth switching circuit, and the other electrode terminal is connected to a reference potential. 2 input capacitance elements,
The first and third switching circuits and the second and fourth switching circuits are turned on / off at a frequency sufficiently higher than the frequency range of the input signal, the other is turned on in one off section, and the other One is turned on in the off section of
An averaging circuit characterized by that.

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