JPH06188738A - D/a converter - Google Patents

Abstract

PURPOSE:To decrease a pulsating component appearing in an analog output without increasing the time constant of an RC filter by smoothing a pulse-width modulated signal, having pulse width proportional to a converted digital value, through the filter circuit of RC. CONSTITUTION:A series circuit of R1 and C1 is provided between the inverted input terminal of an operational amplifier(Amp) which extracts the DC output component of a filter circuit 3 as the analog output 4a by impedance conversion and the output terminal of a pulse width modulating circuit 2. Then a signal which is equal to a pulsating voltage developed across the capacitor C of the filter circuit 3 is supplied to the inverted input terminal of the Amp 4, and consequently the pulsating component appearing in the analog output 4a is canceled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a pulse width modulation circuit which outputs a pulse width modulation signal having a pulse width proportional to a converted digital value at a constant period, and a filter circuit which smoothes this pulse width modulation signal. The present invention relates to a pulse width modulation (hereinafter also referred to as PWM) D / A converter.

In the following figures, the same reference numerals indicate the same or corresponding parts.

[0003]

2. Description of the Related Art FIG. 2 shows a conventional configuration example of a PWM type D / A conversion circuit. In FIG. 2, the PWM circuit 2 has a CP
The pulse width modulation signal 2a proportional to the absolute value of the converted digital data 1a obtained from U1 is converted and output. That is, in the pulse width modulation signal 2a, the high level period T _hi of the constant cycle T is proportional to the absolute value of the converted digital data 1a. For example, digital data 1a obtained from the CPU 1
When the absolute value of changes from 0 to 10000, T _hi / T changes from 0 to 1 in proportion to digital data.

Next, the resistor R and the capacitor C are filled with
The circuit 3 is configured. The pulse output from the PWM circuit 2
The width modulation signal 2a is smoothed by this filter circuit 3.
And T _hiIs converted to a DC signal proportional to / T
The impedance is converted by Amp4 as an operational amplifier.
And output as an analog signal 4a. In this example
Is the non-inverting input terminal of Amp4 with capacitor C and resistor R
Amp4 inverting input terminal and output terminal
It is directly connected to the child. And Amp4 is a capacitor C
The voltage across both ends of the analog is 1: 1 in the form of low output impedance.
The log signal 4a is output.

[0005]

However, according to the D / A conversion circuit of FIG. 2, the filter circuit 3, particularly the resistor R
A pulsating flow occurs due to the filter characteristic determined by the capacitor C. If the RC time constant is increased in order to reduce this pulsating flow, the D / A conversion response becomes slower. Therefore, the present invention can easily solve this problem.
A / A converter is provided.

[0006]

In order to solve the above-mentioned problems, the D / A converter according to claim 1 has a pulse width proportional to the converted digital value (1a, etc.) and is output at a constant period. The pulse width modulated signal (2a etc.) is filtered by the filter circuit (3
In the D / A converter which smoothes the signal through the above) and takes out as an analog output (4a etc.), the pulsating flow signal appearing in the analog output is taken out from the filter circuit, and the pulsating flow signal is canceled to the analog output. It shall be provided with a pulsating flow canceling means for superimposing.

According to a second aspect of the present invention, in the D / A converter of the first aspect, the filter circuit includes a first resistor (R or the like) and a first capacitor (C or the like). The pulsating flow canceling means is an operational amplifier for inputting at least the voltage of the first capacitor to one input terminal (such as a non-inverting input terminal) and extracting the analog output from the output terminal. , A series circuit of a second resistor (R1 or the like) and a second capacitor (C1 or the like) between the other input terminal (the inverting input terminal or the like) and the input end of the pulse width modulation signal to the filter circuit. Of the operational amplifier (Amp4 or the like) inserted therein.

[0008]

The pulse width modulation signal 2a output from the PWM circuit 2 is used to apply a signal having a phase opposite to that of the pulsating flow generated by the filter circuit 3 to the impedance converter 4, thereby generating a pulse generated at the output of the impedance converter 4. Cancel the flow,
Obtain a stable DC signal.

[0009]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
is there. Comparing FIG. 1 with the conventional circuit example of FIG.₁
And capacitor C₁The serial circuit of the output terminal of the PWM circuit 2
And the inverting input terminal of Amp4. here
Resistance R₁And capacitor C ₁The series circuit is the PWM circuit 2
By-passing the AC component of the pulse width modulated signal 2a which is the output of
Let Therefore, this signal is inverted and amplified by Amp4.
At the same time, the amplification factor is the pulsating current generated by the filter circuit 3.
The output pulsating current is canceled by selecting the level.

[0010]

As described above, the pulsating current appearing in the analog output is canceled by using the signal having the opposite phase to the pulsating current generated in the filter circuit for smoothing the pulse width modulation signal having the pulse width proportional to the converted digital value. In order to suppress the output pulsating flow, it is possible to provide a D / A converter capable of high-speed response without slowing the response of the filter circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration as an embodiment of the present invention.

FIG. 2 is a conventional circuit diagram corresponding to FIG.

[Explanation of symbols]

 1 CPU 1a Digital data 2 Pulse width modulation circuit (PWM circuit) 2a Pulse width modulation signal (PWM signal) 3 Filter circuit R, R1 Resistance C, C1 Capacitor 4 Operational amplifier (Amp) 4a Analog output

Claims (2)

[Claims] 1. A D / A converter for smoothing a pulse width modulation signal, which has a pulse width proportional to a digital value to be converted and is output at a constant period, through a filter circuit and takes out as an analog output, wherein: A D / A converter comprising pulsating flow canceling means for taking out a pulsating flow signal appearing in an analog output and superimposing it on the analog output so as to cancel the pulsating flow signal. 2. The D / A converter according to claim 1, wherein the filter circuit is composed of a series circuit of a first resistor and a first capacitor, and the pulsating flow canceling unit is at least the first circuit. An operational amplifier for inputting the voltage of a capacitor to one input terminal and extracting the analog output from the output terminal, wherein a second amplifier is provided between the other input terminal and an input end of the pulse width modulation signal to a filter circuit. A D / A converter comprising an operational amplifier in which a series circuit of a resistor and a second capacitor is inserted.