JPS5957285A - Video signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing device, and particularly to a video signal processing device, for example, two
A device is installed that superimposes video signals from two personal computers and converts them into a composite video signal that can be displayed on a display device.

Conventionally, it has been put into practical use to connect a so-called personal computer and a CRT display and display data output from the personal computer on the CRT display.

By the way, there have been cases where data from two personal computers are desired to be superimposed and displayed on a CRT display. In such a case, there is no problem if different colors are superimposed, but if the same colors are superimposed, there is a possibility that a problem may arise in which the data becomes indistinguishable on the screen. For example, when graphic data such as a bar graph and character data are superimposed, if the character data has the same color as the graphic data, the characters will not be readable on the screen.

Therefore, the main purpose of this invention is to provide an image in which the data from each computer can be clearly distinguished on the screen even when the same colors are superimposed and displayed. An object of the present invention is to provide a signal processing device.

To summarize, this invention subtracts the video signal output from one of two computers from the video signal output from the other computer, and adds the subtracted portion to the video signal output from the other computer. The output video signal is set to a different level from the video signal output from one computer and interpolated, and a contrast i. is applied between the display contents from each computer.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 1 is a block diagram C showing one embodiment of the present invention. In the figure, a personal computer 1 outputs three primary color signals (R, GI, Bl>.
The primary color signal is applied to one input of the field reduction circuit 3. Further, the personal computer 1 outputs a horizontal synchronization signal and a vertical synchronization signal, and the personal computer 2 outputs a horizontal synchronization signal and a vertical synchronization signal.
given to.

This personal computer 2 is a computer that is externally synchronized, and outputs data in synchronization with a horizontal synchronization signal and a vertical synchronization signal from the personal computer 1. That is, the personal combination 1 and 2 output three primary color signals (R2, G2°82) that are synchronized with the three primary color signals (R2°e, BT). These three primary color signals (B2, G2, R2) are given to the other input of the reduction circuit 3.

The reduction circuit 3 receives the signal R+ as shown in FIG.

G7. Buffers 31a and 31b to which B+ is given.

31G, and AND gates 32a, 32b each having one input of these buffers 31a, 31b, and 31C.
, 320 and the AND gates 1-32a, 32b by inverting the polarities of the signals R2, G2, and B2.

32C, and inverters 33a, 33b, and 330 for supplying signals to the other inputs of the input terminals 32C and 32C, respectively. Therefore, Δ
A signal (RI R2) obtained by subtracting the signal R2 from the signal R+ is output from the N[) goo 1-328. Also,
AND game 1-32 From b, signal G, from (=signal 0
A signal (GI G2) from which 2 is subtracted is output. Also, from AND goo 1 to 320, from Shinguchi B, to signal B
A signal (B, -82') with 2 subtracted is output. Furthermore, the fraud reduction circuit 3 includes inverters 33a, 33b,
330, the signal 11z with the H nature inverted,
Inverter 34 for returning Gz, 82 to its original polarity
a , 341> , 34c. The signals fs (RI R2), (G, G2), (B
I82) is applied to one input of the adder circuit 4.

In addition, the signals R2, G2, B output from the reduction circuit 3
2 is applied to the other input of the itching circuit 4.

As shown in FIG. 2, the addition circuit V84 receives the signal (RI--
R2), (GI G2), (B+ -Bz
) is received as one input of ~ OR goo 1-41a
, 41b, 41c, etc., the levels of the signals Rz, Gt, 82 are reduced to a predetermined level (OR)-41a
.

A variable resistor 42a for supplying signals to 41b and 41C.

42b, 420. Therefore, this adder circuit 4 generates a signal Rz reduced to a predetermined level in the part from which the signals R2, G2, and B2 are subtracted by the defielding circuit 3:
, G2, and B2 are interpolated. The output of the adder circuit 4 is given to the converter circuit 5.

The conversion circuit 5 includes a buffer 51a as shown in FIG.
, 51b, 51c, and an inverter 52a.

52b, 52C, and a resistance matrix circuit 53.

Therefore, this conversion circuit 5 converts the three primary color signals supplied from the adder circuit 4/31 into a 1rl11 degree signal Y and a color difference signal (
RY), (BY). The output of the conversion circuit 5 is transmitted to the emitter followers 9a and 9 as shown in FIG.
b and 9c to the one-coder circuit 6.

The encoder circuit 6 includes various circuits as shown in FIG. 3, and converts the luminance signal and color difference signal provided from the conversion circuit 5 into a video signal that is a composite of the luminance signal and carrier color signal. A horizontal synchronization signal and a vertical synchronization signal from the personal computer 1 applied via an OR gate 7 are superimposed on the output of this 1 encoder circuit 6 and applied to the emitter follower 8 . From this emitter follower 8, NTS
A composite video signal of C is output.

Note that the output of the R-Y, B-Y mixing circuit in the encoder circuit 6 is fed back via the bandpass filter 46 and the capacitor C to the mixing circuit for the luminance signal and the mts signal.

This bandpass filter 46 is provided to remove harmonic noise components from the composite +pm signal.

FIG. 4 shows the output signals R1 of the personal computer 1,
It is a waveform chart showing G+' and B+. FIG. 5 is a waveform diagram showing the output signals 112, G2, and B2 of the personal computer 2. Figure 6 shows the output signal of the frame loading circuit (
R+ R2) , (Gl (32>, (81B2
) is one waveform diagram. FIG. 7 is a waveform diagram showing the output signal of the addition circuit 4. For convenience of explanation, FIGS. 4 to 7 are shown so that their respective time axes correspond to each other.

The operation of an embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

First, a horizontal synchronization signal and a vertical synchronization signal are provided from the personal computer 1 to the personal computer 2. The personal computer 2 adjusts its internal synchronization to this horizontal synchronization signal and vertical synchronization signal. Next, the n reduction circuit 3 outputs the output signal R+ of the personal computer 1.
, Gl , B+ , personal computer 2
Subtract the output signals R2eGz and Bt, and the signals R1 and G5
．． Signals R2, G2, and B2 are extracted from B+ (see Figure 6).

On this extracted portion, the adder circuit 4 superimposes a signal obtained by suppressing the output signals @R2, G2, B2 of the burner computer 2 to the level formed by the variable resistors 42a, 42b, 42c (see Fig. 7). .

As a result, a load mark is added to the output signal of the personal computer 1 and the output signal of the burner computer 2. Therefore, if this contrasted three primary color signals are converted into a composite video signal and displayed on a CRT display, even if the superimposed parts are the same color, the data from the personal computer 1 and the purple computer 2 can be It is possible to clearly distinguish between the data of

Incidentally, in order to increase the contrast 1- as described above, the output signal of the personal computer 2 may be amplified to a predetermined level and then mixed. Alternatively, the output signal of the personal computer 1 may be subtracted from the output signal of the personal computer 2, and the output signal of the personal computer 1 reduced or amplified to a predetermined level may be superimposed on the subtracted portion.

. As described above, according to the present invention, the video signal of the other computer is subtracted from the video signal of the one computer, and the video signal of the other computer is added to the subtracted portion at a level different from that of the video signal of the one computer. Since the two computers overlap each other, even if data of the same color is output from both computers at the same time, they can be clearly distinguished on the display screen.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing the subtraction circuit 3 and addition circuit 4 not shown in FIG. 1 in more detail. FIG. 3 is a circuit diagram showing the conversion circuit 5 and encoder circuit 6 shown in FIG. 1 in more detail. FIG. 4 is a waveform diagram showing output signals of the personal computer 1. FIG. 5 is a waveform diagram showing the output signal of the personal computer 2. As shown in FIG. FIG. 6 is a waveform diagram showing the output signal of the subtraction circuit 3. FIG. 7 is a waveform diagram showing the output signal of the adder circuit 4. In the figure, 1 and 2 are personal computers, 3
4 represents a subtraction circuit, 4 represents an addition circuit, 5 represents a conversion circuit, and 6 represents an encoder circuit. Patent applicant: Sharp Corporation Figure 4, District 5, Figure 6, Figure 7, 649-

Claims (1)

[Claims] An ff1l video signal having three primary color signals for displaying input data as an image, a horizontal periodic signal,
The ff11 computer outputs a vertical synchronization signal, and the first
a second computer that outputs a second video signal having a U3 primary color signal in synchronization with a horizontal synchronization signal and a vertical synchronization signal from the computer; means for subtracting the second or first video signal from the portion of the first or second video signal from which the second or first video signal is subtracted; A video signal processing device comprising means for interpolating a video signal at a level different from that of the video signal, and means for converting the three primary color video signals from the interpolation means into a composite video signal.