JPS5955651A - Circuit for reducing sound volume - Google Patents

Abstract

PURPOSE:To attain the reduction of sound volume even if noise or the like are received, by controlling a voice output level by outputs from a circuit detecting synchronization or asynchronization of a received and reproduced clock, and a circuit detecting received electric field strength. CONSTITUTION:A receiver inputs a receiving wave and a demodulating circuit 1 reproduces a clock from the received signal. The reproduced clock is inputted to a phase locking circuit 2 and asynchronization detecting circuit 3 detects the synchronization or asynchronization between the input and output clocks. The circuit 2 is synchronized with only input clocks in a specific frequency range. On the other hand, input electric field to the receiver is detected by an electric field strength detecting circuit 4. Outputs from these two detecting circuits are inputted to an AND circuit 5 and the output level of a voice amplifier circuit 6 is controlled by the output of the circuit 5. Consequently, voice can be reduced even if an unnecessary waves such as noise is received in addition to the absence of a received input, so that highly reliable sound volume control can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a volume reduction circuit used in digital communications.

Conventional volume reduction circuits reduce the volume of the audio output when the received electric field strength of the receiver is below a certain value, and output the audio at the normal volume when it is above that value, reducing noise etc. This has the disadvantage that the volume is not reduced when unnecessary waves are received.

The purpose of the present invention is to detect not only the receiver input electric field strength but also the synchronization state of the clock reproduced from the received signal and the output clock obtained by inputting this clock to a phase synchronization circuit, and to detect these two detected outputs. The objective is to perform more reliable volume control.

In the present invention, even when the received electric field is stronger than a certain value, when unnecessary waves such as noise are received, the clock regenerated from the received signal and the clock are input to the phase synchronization circuit, and the resulting output clock is synchronized. Taking advantage of the fact that the signal is off, the volume is reduced when unnecessary waves such as noise are received.

The figure shows an embodiment of the volume reduction circuit of the present invention.

In this figure, 1 is a demodulation circuit, 2 is a phase synchronization circuit, 3 is a synchronization detection circuit, 4 is a field strength detection circuit, 5 is an AND circuit, 6 is an audio amplification circuit, and 7 is a speaker.

In the figure, a received wave is input to a receiver, and a clock is regenerated from the received signal in a demodulation circuit I.

The regenerated clock is input to the phase synchronization circuit 2, and an out-of-synchronization detection circuit 3 detects whether the clock is synchronized or not with the resulting output clock. Here, it is assumed that the phase synchronization circuit 2 can be synchronized only with respect to an input clock of a certain specific frequency. The electric field input to the receiver is detected by an electric field strength detection circuit 4.

The outputs of these two detection circuits are input to an AND circuit 5, and the output level of the audio amplifier is controlled by the output of the AND circuit. Here, if an electric field of a certain value 7 or more is input to the receiver, the output of the field strength detection circuit 4 will be II I. If it is less than I+V, the output will be 11011, and if the regenerated clock and the phase synchronization circuit are synchronized. If it is, the output of the out-of-synchronization detection circuit 3 is 1'1°1, and if it is out of synchronization, the output is II Q II l. Now, if we consider the case where a desired wave with a received field strength of V or more is received, the output of the field strength detection circuit 4 reaches 1°. Also, the clock regenerated from the received signal and the output clock of the phase synchronization circuit 2 are not synchronized. The output of the out-of-synchronization detection circuit 3 is °1.
1''. Therefore, the AND circuit output 5 is II I H
The audio amplifier 6 then outputs the normal volume.

On the other hand, if unnecessary waves such as noise with an electric field strength of 7 or more are received, the electric field strength will be multiplied! The output of 84 becomes 1゛1'', but the frequency component of the regenerated clock is random and the lock does not fall within the synchronization pull-in range of the phase synchronized circuit 2, so the regenerated clock and the output clock of the phase synchronized circuit 2 are not synchronized. Therefore, the output of the out-of-synchronization detection circuit 3 is °゛011.
Then, the output of the AND circuit 5 is also II Q n, so the audio amplifier output level is controlled and the volume is reduced.

When the received electric field is below V, the output of the electric field strength detection circuit 4 becomes IIQ+'', and the output of the AND circuit 5 also becomes 110N, so that the audio amplifier output level is controlled and the volume of the humming is reduced.

According to the present invention, the volume can be reduced even when unnecessary waves such as loud noise are received only when there is no reception input, and more reliable volume control can be performed.

[Brief explanation of the drawing]

The figure is a diagram showing the configuration of a volume reduction circuit according to the present invention. In the figure, 1 is a demodulation circuit, 2 is a phase synchronization circuit, 3-3 is a synchronization error detection circuit, 4 is an electric field strength detection circuit, and 5 is a phase synchronization circuit.
is an AND circuit, 6 is an audio amplification circuit, and 7 is a speaker. 4-

Claims (1)

[Claims] A digital communication receiver includes a first detection circuit that detects a synchronization or asynchronous state of a received and recovered clock, and a second detection circuit that detects a received electric field strength. A volume reduction circuit characterized in that the output level of audio is controlled by the output of the second detection circuit.