JPH0528926B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a tone squelch circuit suitable for use in a receiver of a wireless communication system such as a cellular radio telephone.

[Background of the invention]

2. Description of the Related Art Conventionally, there have been known radio receivers, such as cellular radio telephones, that use tone signals to control squelch. In a wireless communication system using such tone signals, a predetermined specific tone signal is sent from the transmitter to the receiver of the other party to be talked to, and the receiver of the other party receives the tone signal. uses that specific tone signal to turn on the audio circuit and adjust the listening tone. The circuit for this purpose is a tone squelch circuit.

The tone squelch circuit detects when there is a specific tone signal in the received radio waves, turns on the audio signal, generates sound from the received radio waves from the speaker, and also detects when there is a specific tone signal in the received radio waves. If not, reverse the audio circuit.
Turn it off to prevent noise from the speakers.

By the way, there are a plurality of types of tone signals, and these different types may use frequencies that are very close to each other, such as 5970Hz, 6000Hz, and 6030Hz, for example. In such a case,
In the tone squelch circuit, a bandpass filter with a large Q must be used in order to clearly distinguish and detect these tone signals.
However, bandpass filters have temperature characteristics,
In addition, since characteristics change over time, it is necessary to compensate for these changes, which increases the number of parts in the tone squelch circuit, complicates the circuit configuration, and increases the cost of the radio receiver. It will cause a stir.

On the other hand, for example, in an AM stereo device, a muting circuit for selectively mutating a coherent detection output signal is used as a PLL (phase locked loop) that is supplied with an input signal to be coherently detected and forms a carrier wave for coherent detection. There is a known technology that detects the locked state of a lock loop (lock loop) circuit and controls a muting switch depending on whether or not it is locked (Japanese Patent Application Laid-open No. 1983-1979-1).
Publication No. 52236).

To briefly explain such a muting circuit with reference to FIG. 6, an input signal from an input terminal 1 is supplied to a PLL circuit 3 via a limiter 2.
When the PLL circuit 3 is locked to the input signal, it outputs a signal whose phase is shifted by π/2 with respect to the input signal. The output signal of this PLL circuit 3 is phase-shifted by π/2 in a phase shift circuit 5, and is supplied to a multiplier circuit 4 together with the output signal of the limiter 2.

When the PLL circuit 3 is locked to the input signal, the output signal of the phase shift circuit 5 is in phase with the input signal, and the multiplier circuit 4 outputs a DC voltage of a predetermined level or higher. However, when the PLL circuit 3 is not locked to the input signal, no DC voltage is obtained from the multiplication circuit 4, or a DC voltage at a level lower than the predetermined level is output.

The output of the multiplication circuit 4 is supplied to a comparator 22 via a low pass filter 6. The comparator 22 compares the input voltage from the low-pass filter 6 with the reference voltage E at the predetermined level, and when the input voltage is higher than the reference voltage E, for example, a high level control voltage is output and the muting switch 9 is output. In the opposite case, a low level control voltage is output and the muting switch 9 is turned off.

On the other hand, the output signal of the PLL circuit 3 is supplied as a carrier wave to the multiplication circuit 8, and the input signal from the input terminal 1 is periodically detected.

Therefore, an input signal is supplied from input terminal 1,
Assuming that PLL circuit 3 is locked to this,
The multiplier circuit 8 performs synchronous detection on this input signal to obtain an audio signal. Since the muting switch 9 is on at this time, this audio signal is output from the output terminal 10 via the muting switch 9. On the other hand, if there is no input signal at the input terminal 1, or if there is an input signal but the PLL circuit 3 is not locked to it, no audio signal is obtained from the multiplier circuit 8, and noise etc. However, since the muting switch 9 is off at this time, unnecessary signals such as noise are blocked.

Here, PLL circuits generally have very high Q
It locks to an input signal at a different frequency, and also locks to an input signal of a different frequency. Therefore, by applying the principle of the above-described muting circuit to the tone squelch circuit of a radio receiver, it becomes possible to reliably discriminate between the plurality of types of tone signals that are very close to each other as described above.

By the way, whether or not the PLL circuit 3 is locked is also influenced by the S/N of the tone signal. Therefore, the squelch level should be set in consideration of this S/N ratio, and for this purpose, an adjusting means for making the reference voltage of the comparator circuit 22 variable is provided. As a means for this adjustment, it is possible to use a so-called mechanical rotating volume, but in recent years, with the development of microcomputers and digital technology,
Wireless communication devices are also beginning to have built-in microcomputers, and in such cases, from the standpoint of the external design of the wireless communication device, it is not desirable to use a rotary volume, and it is desirable to use an electronic volume. The same applies to the squelch level adjustment means. However, with the above-mentioned conventional technology, it is extremely difficult to meet such requirements.

Also, since processing is done in an analog manner,
This becomes a big problem when the circuit size becomes large, such as car phones and portable wireless phones installed in cars.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a tone squelch circuit which eliminates such problems, allows the squelch level to be adjusted digitally, and allows the constituent circuits to be converted into digital circuits.

[Summary of the invention]

To achieve this objective, the present invention counts the lock period of the PLL circuit to the tone signal in a certain period, compares the obtained count value with a reference count value, and adjusts the mute circuit according to the comparison result. It is unique in that it can be controlled on and off.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the tone squelch circuit according to the present invention, in which 1 is an input terminal, 9 is a mute circuit, 10 is an output terminal, and 29 is a block diagram showing an embodiment of the tone squelch circuit according to the present invention.
FM detection circuit, 30 is BPF (band pass filter), 31 is rising edge detection circuit, 32 is PLL
circuit, 33 is an oscillation circuit, 34 is a timing circuit,
35 is an up-down counter, 36 is an R-S flip-flop, 37 to 39 are AND gates, 40
is an inverter, 41 is a timing circuit, 42 is a register, 43 is a counter, 44 is a latch circuit, 4
5 is a comparator.

In the figure, when receiving an audio signal,
A signal obtained by frequency multiplexing the audio signal and the tone signal a and performing FM modulation is input to the input terminal 1 and detected by the FM detection circuit 29. The output signal of the FM detection circuit 29 is sent to the mute circuit 9 and the BPF 30.
The tone signal a is separated by the PBF 30. Tone signal a has frequencies of 5970Hz, 6000Hz,
There are three types of 6030 Hz, and the BPF 30 has a pass band that allows any one of these to pass. Here, it is assumed that the tone signal a of 6000 Hz is passed.

Therefore, PLL circuit 32 passed through BPF 30.
It will lock to the tone signal a of 6000 Hz, but in order to determine whether the PLL circuit 32 has locked to the tone signal a, the timing circuit 3
4. A lock detection circuit A is provided which includes an up-down counter 35, an R-S flip-flop 36, AND gates 38 and 39, and an inverter 40.

The operation of this lock detection circuit A will be explained below with reference to FIG. In this figure, signals corresponding to those in FIG. 1 are given the same reference numerals.

The timing circuit 34 receives the output signal of the PLL circuit 32 and the pulse f from the oscillator 33, and generates a window signal b that becomes "1" (high level) in a phase range of ±20° centered on the rising edge of this output signal. generate. This window signal b is supplied as a gate pulse to an AND gate 39 and an AND gate 38 after being inverted by an inverter 40 . Also, BPF
The tone signal a separated at 30 is supplied to a rising edge detection circuit 31, the rising edge of which is detected, and a rising pulse a' representing this is supplied to AND gates 38 and 39.

Therefore, the AND gate 39 outputs "1" of the window signal b.
The AND gate 38 allows the rising pulse a' within the period to pass, and the AND gate 38 passes the rising pulse a' within the "0" period of the window signal b. The output pulse c of the AND gate 39 is up-counted by the up-down counter 35, and the output pulse d of the AND gate 38 is counted up.
is counted down by an up-down counter 35. When the count value reaches a predetermined value (here, 16), the up-down counter 35 generates a set pulse to set the R-S flip-flop 36, and the count value reaches another predetermined value (here, 16). 0), a reset pulse is generated to reset the R-S flip-flop 36.

In a lock detection circuit that operates as described above,
When the PLL circuit 32 is completely locked to the tone signal a, the rising edge of the tone signal a is almost in the "1" period of the window signal b, and the up-down counter 35 counts up. This up-down counter 35 has a count value of
When it reaches 16, the R-S flip-flop 36 is set, and when a certain value is reached thereafter, that value is held and the up-count is stopped. Therefore,
When PLL circuit 32 is completely locked to tone signal a, R-S flip-flop 36 is held set and its Q output, i.e.
The lock detection signal e of the PLL circuit 32 is held at "1".

However, even if the PLL circuit 32 is locked to the tone signal a, if the received field strength of the radio receiver decreases and the S/N of the tone signal a output from the BPF 30 is low, the rising edge of the tone signal a There are cases where the edge is outside the "1" period of window signal b. That is, in such a low S/N state,
The rising edge of tone signal a is “1” of window signal b
Whether it is within the period or not is a matter of probability. In order to determine whether the PLL circuit 32 is locked to the tone signal a, it is only necessary to determine whether the rising edge of the tone signal a is in the "1" period of the window signal b, and the AND gate 39, 38 output pulses c, d set the R-S flip-flop 36,
All you have to do is reset it (thereby, the lock detection signal e becomes "1" when it is locked, and "0" when it is not locked), but if you do it this way, it will cause a low S/N as described above. In this state, even though the PLL circuit 32 is locked, the R-S flip-flop 36 is reset and the lock detection signal e becomes "0", making the operation ambiguous.

The up-down counter 35 is for reducing such ambiguity, and is used for tone signal a.
Even if the rising edge of the window signal b is out of the "1" period of the window signal b, if there is a high probability that this rising edge is within the "1" period of the window signal b, the PLL
It is assumed that the circuit 32 is locked to the tone signal a, and the lock detection signal e is set to "1". A circuit that acts like this is generally called a random walk filter.

When the S/N is low, the lock signal e is stochastically in the "1" state and the "0" state, as shown in FIG. This lock detection signal e is supplied as a gate pulse to the AND gate 37, and the oscillation circuit 33
Gate a 1kHz pulse f from .

The output pulse g of the AND gate 37 is the counter 4
3, and the 100 msec "1" period of the timing signal h supplied from the timing circuit 41 is counted. The count value of the counter 43 during this period is latched in the latch circuit 44 in synchronization with the rising edge of the timing signal h, and the comparator 45 compares this latched count value with the reference count value stored in the register 42. be compared. This comparator 45 outputs a signal of "1" when the latched count value≧the reference count value, and thereby the mute circuit 9 is released from mute.

Incidentally, the count value latched by the latch circuit 44 varies probabilistically depending on the S/N ratio of the received signal. The average value and variance of this count value with respect to S/N are shown in Figure 4, and the probability density function is as follows, where m is the average value and σ is the variance.
The count value is expressed as follows and has a normal distribution.

p(x)=1/σ√2πe×p[−(x−m) ² /2σ
² ] Therefore, the probability that the mute circuit 9 will be released from mute using the reference count value as a parameter is expressed as follows.

PP(y)=∫ ^y _-∞ p(x)dx Here, y is a value determined by the S/N and the reference count value. The probability of mute cancellation of mute circuit 9 with respect to S/N is calculated based on the standard count value of 60, 75, 90.
Fig. 5 shows the results for each of the above.

In this way, by changing the reference count value stored in the register 42, the probability of canceling mute depending on the S/N also changes. Therefore,
By adjusting this reference count value, it is possible to set the squelch level in consideration of the S/N ratio of the tone signal, and furthermore, this squelch level can be adjusted digitally.

Note that in this embodiment, the timing circuit 4
1, register 42, counter 43, latch circuit 4
4 and the comparator 45 can of course be realized by microcomputer software. In addition, if the processing speed of the microcomputer is fast, the PLL circuit 32 and the lock detection circuit A
This can also be realized using software, and the entire tone squelch circuit can be converted into a digital circuit, making it suitable for LSI implementation, resulting in a significant reduction in the number of parts and circuit scale.

〔Effect of the invention〕

As explained above, according to the present invention, since the squelch level can be adjusted digitally, a rotary volume is no longer necessary, and restrictions on the design of a wireless receiver are greatly alleviated. It is now possible to convert the circuit into a digital circuit, making it suitable for LSI implementation, making it possible to significantly reduce the number of parts and scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the tone squelch circuit according to the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of this embodiment, and FIGS. 4 and 5 are diagrams of this embodiment. A graph showing the performance, and FIG. 6 is a block diagram showing an example of a conventional muting circuit. 1...Input terminal, 9...Mute circuit, 10...
...Audio signal output terminal, 30...Band pass filter, 31...Rising edge detection circuit, 32
...PLL circuit, 33 ... oscillation circuit, 34 ... timing circuit, 35 ... up-down counter,
36...R-S flip-flop, 41...timing circuit, 42...register, 43...counter, 44...latch circuit, 45...comparator, A...
...Lock detection circuit.

[Claims]

1. An optical communication method in an optical communication system having one or more working lines and one protection line between two stations, each of which includes two optical fiber transmission lines whose transmission directions are opposite to each other. ,
If deterioration is detected in a semiconductor laser as a transmission light source on any of the working lines, the station will switch the line related to the semiconductor laser deterioration to a protection line, and
While the fault detection information is transmitted to the other station via the optical fiber transmission line for transmission of the line related to semiconductor laser deterioration, the other station detects the fault detection information and detects the semiconductor laser. An optical communication system characterized by switching deteriorating lines to backup lines. 2. The optical communication system according to claim 1, wherein deterioration of the semiconductor laser is detected from the magnitude of the semiconductor laser drive current. 3. The optical communication system according to claim 1, wherein deterioration of the semiconductor laser is detected from the magnitude of the optical output level of the semiconductor laser.