JPS5811138B2 - PLL unlock signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an unlock signal detection circuit for a phase-locked loop (hereinafter referred to as PLL) used for obtaining a local oscillation frequency signal or a carrier wave signal in a wireless device such as a transceiver.

In transceivers using PLL, when switching channels, unpleasant noise is generated during reception, and unnecessary radiated signals are generated during transmission, so it is necessary to operate muting or stop transmission during that time. There is.

The present invention relates to a PLL unlock signal detection circuit for detecting an unlock signal used in such a case.

Figure 1 is a general block diagram of a transceiver using a PLL, in which PLL1 includes a reference oscillator 2, a reference frequency divider 3,
Consisting of a variable frequency divider 4, a phase comparator 5, a low-pass filter 6, a voltage controlled oscillator 7 (hereinafter referred to as vCO), and a mixer 8, the signal obtained from the PLL is sent to a mixer 9.10 when receiving the signal. In addition, it is mixed with the received signal to obtain an intermediate frequency signal, and at the time of transmission, it is added to the modulator 11, modulates the audio signal from the microphone, and transmits it from the antenna 12.

In this case, the phase comparator 5 detects an unlock signal.

FIG. 2 shows a specific example of the phase comparator 5, which includes input terminals a and b connected to the reference frequency divider 3 and variable frequency divider 4, respectively, 1) consists of a large number of logic circuits 13, 13, . . . connected to the circuit.

Compare the phase difference between the signals applied to input terminals a and b (Fig. 5 A and B, and if there is a phase difference, a signal (Fig. 5 C) will be generated from output terminal C, and if there is no phase difference, the signal will go high. I'm trying to make it impedance.

At the same time, an unlock detection circuit 14 is provided to detect an unlock signal (FIG. 5E) and mute the amplifier of the transceiver or stop transmission.

There are various conventional unlock signal detection circuits 14, and one example, as shown in FIG. 3, includes a first field effect transistor 17 connected to a NAND circuit 15 via an inverter 16, a time constant circuit 18, A second field effect transistor 20 is connected to the first field effect transistor 17 via an inverter 19. An output signal (FIG. 6E) is generated depending on the phase difference.

Then, the potential of the time constant circuit 18 increases (FIG. 6D), and when the pulse width of the output signal of the NAND circuit 15 reaches a certain value,
Threshold voltage ZDD of inverters 19, 19
Since the second field effect transistor 20 is turned on after exceeding the voltage, an unlock signal (H in FIG. 6) is obtained at the terminal.

However, the unlock signal has large variations due to off-leakage current of the transistor, input leakage current, on-resistance, and threshold voltage.

The present invention, which eliminates this drawback, is shown in FIG. 4.

That is, an AND circuit 21 whose input terminals are connected to the reference frequency divider 3 and the phase comparator 5, a D flip-flop 22 controlled by the output of the AND circuit 21, and an RS flip-flop 23 connected to the D flip-flop. , an OR circuit 24 connected to supply the Q output of the D flip-flop 22 and the Q output of the RS flip-flop 23 as a reset signal to the subsequent stage of the reference frequency divider 3, and a stage to which the reset signal is applied. The AND circuit 25 has an input side connected to the reference frequency divider 3 and an output side connected to the r terminal of the RS flip-flop 23.

Next, to explain the operation, when there is no phase difference between the two signals applied to the reference frequency divider 3 and the variable frequency divider 4, the output of the terminal e of the phase comparator 5 is level "0". However, if a phase difference occurs between the two signals, a pulse signal of level "1" (FIG. 7E) is generated at terminal e.

The pulse width of this pulse signal increases as the phase difference increases.

Since the pulse signal (Fig. 7 E) is inhibited by the pulse signal (Fig. 7 Qn+1) from the qn+1 stage of the reference frequency divider 3, the pulse width of the pulse signal (Fig. 7 E) is When it is small, the AND circuit 21 is stopped and no signal is applied to the D flip-flop 22.

When the pulse width of the pulse signal (FIG. 7E) exceeds a certain value, the pulse signal (FIG. 7 Qn+1) can no longer inhibit the signal, and the AND circuit 21 obtains the signal (FIG. 7F).

Said signal (FIG. 7F) inverts the D flip-flop 22, and the q terminal produces a level "1" signal.

(Figure 7G). Thereby the RS flip-flop 23
The S terminal of is at level ``1'', and the q terminal is also at level ``1''.
becomes.

(Figure 7Q). This signal is detected as an unlock signal.

This unlock signal is applied to the r terminal of the RS flip-flop as a signal from the reference frequency divider 3 [Fig. 7 QD1゜QD2
] is added via the AND circuit 25 (R in FIG. 7), and R
This is maintained until the S flip-flop 23 is reset.

By the way, the signal from the D flip-flop 22 is applied to the r terminal of the reference frequency divider 3 (DtjQD2,
It is reset every time the q terminal of the D flip-flop 22 becomes level "1".

Therefore, after the terminal of the phase comparator 5 reaches the level ``1'' at the very end, the reference frequency divider 3 counts a predetermined number to determine the level of the q terminal of the RS flip-flop 23, that is, the unlock signal. (Fig. 7 Q) disappears.

As described above, the PLL unlock signal detection circuit of the present invention performs pulse width discrimination on the phase difference signal detected by the phase comparator using the output signal of an arbitrary stage of the reference frequency divider, and converts these signals into logic means. In addition, since the phase difference signal is extended, an unlock signal of a constant desired magnitude can always be obtained without being affected by off-leakage current of the transistor.

Furthermore, since the processing is performed digitally, the number of external circuits can be reduced and integration is facilitated.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a general transceiver using PLL, Fig. 2 is a circuit diagram of the phase comparator shown in Fig. 1, Fig. 3 is a conventional unlock signal detection circuit diagram, and Fig. 4 is a diagram of a conventional unlock signal detection circuit. The unlock signal detection circuit diagram, FIG. 5, FIG. 6, and FIG. 7 are output signal waveform diagrams of each part. 2... Reference frequency generator, 3... Reference frequency divider, 4... Variable frequency divider, 5.
... Phase comparator, 21 ... AND circuit,
22...D flip-flop, 23...
・RS flip-flop.

Claims (1)

[Claims] 1 a reference frequency generator, a reference frequency divider that divides the signal from the reference frequency generator, a variable frequency divider controlled by a channel selector, the reference frequency divider and the variable frequency divider. a phase comparator that detects a phase difference between an output signal and a frequency divider, and performs pulse width discrimination on the phase difference signal detected by the phase comparator using an output signal of an arbitrary stage of a reference frequency divider; When the phase difference signal is greater than or equal to a desired pulse width, the phase difference signal and the output signal of any stage of the reference frequency divider are applied to a logic means to expand the phase difference signal and generate an unlock signal. This is a PLL unlock signal detection circuit.